Abstract: A method of forming an intermediate semiconductor structure as part of a BiCMOS process to provide for improved anti-punch-through (APT) protection and improved threshold-voltage (Vt) adjustment for the MOS devices of the structure. The method includes the fabrication of a split polysilicon layer and the introduction of APT and Vt related carriers after formation of the gate oxide layer. The intermediate structure includes the gate oxide layer and a protective amorphous silicon layer formed on the surface of the gate oxide layer in an in situ process. The protective amorphous structure is formed to protect the integrity of the gate oxide layer during subsequent acid washes associated with the BiCMOS process. The amorphous layer may be deposited in a thickness substantially less than that associated with prior spilt polycrystalline silicon processes. This allows for introduction of the APT and Vt related carriers using relatively standard implanting equipment.