Patents by Inventor Thomas A. Feltner

Thomas A. Feltner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6978541
    Abstract: Disclosed is apparatus to enhance thermal energy transfer from a heater to a DUT in IC handler systems. The pick-up head of an IC handler system is made of metal blocks in maximal thermal contact, and further includes an electrically resistive and thermally conductive layer. The electrically resistive layer provides ESD protection to the DUT. The preferred apparatus uses a collapsible billows suction cup to secure, pick-up, and align DUTs.
    Type: Grant
    Filed: October 1, 2002
    Date of Patent: December 27, 2005
    Assignee: Xilinx, Inc.
    Inventors: Thomas A. Feltner, John C. Marley
  • Patent number: 6956390
    Abstract: An test block includes a box-like body and four rails extending from side edges of the body. During thermal testing, the test block is mounted between a test head and a test socket such that the rails provide a thermal path between the test block body and contact pads formed on the test socket. In this manner the rails emulate the thermal path formed by the metal leads extending from a conventional Quad Flat Pack Integrated Circuit (QFP IC), thereby reliably duplicating the actual thermal path of the QFP IC. The test block is mounted on the test system and its temperature is measured before and after testing QFP IC devices. Confirming that the test block is within test temperature specifications before and after the QFP-IC test procedure provides a highly reliable verification that the QFP-IC's actual test temperature is within the test temperature specifications.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: October 18, 2005
    Assignee: Xilinx, Inc.
    Inventors: Thomas A. Feltner, James S. Aylett, John C. Marley, Thomas A. Gallagher
  • Patent number: 6856862
    Abstract: A light curtain safety system for a semiconductor device handler that includes a programmable control unit and a robot mechanism that is selectively operated in response to signals generated by the control unit. The light curtain safety system includes an apparatus for generating a light curtain such that accessing the robot mechanism requires breaking the light curtain. The light curtain safety system detects an operating state of the semiconductor device handler using signals generated in the control unit, and allows de-activation of the light curtain apparatus only when operating state of the semiconductor device handler is in a predetermined “safe” operating state. When the light curtain apparatus is active and the light curtain is broken, the light curtain safety system causes the semiconductor device handler to terminate power flow to the robot mechanism.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: February 15, 2005
    Assignee: Xilinx, Inc.
    Inventor: Thomas A. Feltner
  • Patent number: 6703852
    Abstract: A low-temperature semiconductor device test apparatus that includes a device tester having a purge box mounted thereon, a low-temperature handler system, and a load board having a IC test socket. The purge box is located between the load board and a support plate of the device tester, and between groups of compressible test pins used to pass test signals to the test socket through conductive traces formed in the load board. The purge box includes rigid outer walls defining a chamber that is located opposite to the test sockets. During low-temperature testing, dry air is pumped into the chamber through conduits formed in the walls of the purge box to prevent the condensation of moisture on conductors formed on the load board and exposed in the chamber. In addition, the purge box resists bending of the load board when semiconductor devices are pressed against the test sockets.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: March 9, 2004
    Assignee: Xilinx Inc.
    Inventor: Thomas A. Feltner
  • Patent number: 6457251
    Abstract: A calibration assembly and method for calibrating the device pick-up heads used in multi-head IC handlers such that all of the device pick-up heads are reliably calibrated to a consistent optimal calibration position. Gauge blocks are provided that greatly simplify the calibration process by holding the movable portion of a device pick-up head in an optimal calibration position relative to the base structure of the device pick-up head while the collar is secured. Each gauge block has base portion for supporting the base structure of the device pick-up head, and a flat contact surface against which the lower surface of the movable portion is pressed. The contact surface is a predetermined distance from the base portion such that when the device pick-up head is mounted on the gauge block, the movable portion is maintained in an optimal calibration position relative to the base structure.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: October 1, 2002
    Assignee: Xilinx Inc.
    Inventors: Thomas A. Feltner, John C. Marley