Abstract: A circuit for connecting lower AC voltage-rated AC-DC power supplies with higher voltage power sources. A power line matching transformer connecting the source to the power supplies needs only to support the self-dissipation and output current mismatch between supplies. The circuit can also protect the line matching transformer from overheating in various fault scenarios.

Abstract: A telescoping dip tube assembly having a first tube which telescopes within a second tube. The exterior surface of the first tube has a first tube stop ring extending outwardly from its exterior surface adjacent its bottom end. The second tube has a second tube stop ring which extends inwardly from its interior surface. When the second tube is lowered over the first tube, the bottom surface of the second tube stop ring engages the top surface of the first tube stop ring, thereby preventing the second tube from separating from the first tube. This arrangement provides the advantage of a telescoping dip tube assembly that is strong and durable and prevents the second tube from falling into a tanker while being loaded.

Abstract: A circuit for connecting lower AC voltage-rated AC-DC power supplies with higher voltage power sources. A power line matching transformer connecting the source to the power supplies needs only to support the self-dissipation and output current mismatch between supplies. The circuit can also protect the line matching transformer from overheating in various fault scenarios.

Abstract: Disclosed is a process for etching semiconductor materials with a high etch rate against an insulator mask using a novel etchant gas mixture. The mixture consists of a chlorocarbon (e.g., CCl.sub.2 F.sub.2, CCl.sub.4 or CCl.sub.3 F), SF.sub.6, O.sub.2 and an inert gas (e.g. He). The preferred gas mixture contains 2/1 ratio of the chlorocarbon to SF6 and the following composition: 1-4% of SF.sub.6, 3-10% of O.sub.2, 74-93% of He and 3-10% of chlorocarbon. The etch rate of silicon (or silicide) against an oxide mask using this etchant gas mixture under normal etching conditions is high, on the order of 30-40. An impressive feature of the process is shape control of trenches by mere manipulation of the RIE system power.

Abstract: Disclosed is the use of metal silicide (e.g. Pt-Si) contacts in boron lightly doped P.sup.- type silicon between two contiguous but not adjacent N.sup.+ type regions instead of employing the usual P.sup.+ implanted or diffused channel stoppers. The invention finds a particularly interesting application in polyimide filled deep trench isolated integrated circuits.The trench sidewalls are coated with an insulating material which is removed from the trench bottom at the all contact etch step. The Pt-Si is formed at the bottom of the trenches at the same time that the device contacts are made.

Abstract: Deep trenches (14,15) are formed according to the desired pattern through the N epitaxial layer (13) and N.sup.+ subcollector region (12) into the P.sup.- substrate (11) of a silicon structure (10). Where a substrate contact is needed, the trenches delineate a central stud (16) or mesa of silicon material. Channel stop regions (18) are formed e.g. by ion implantation of boron atoms at the bottom of trenches, SiO.sub.2 and Si.sub.3 N.sub.4 layers (17,19) are then deposited on the whole structure. A substrate contact mask is applied and patterned to selectively expose one side of the trench sidewalls, the bottom of the trenches adjacent thereto and others areas if desired such as the top surface of the stud. The composite SiO.sub.2 /Si.sub.3 N.sub.4 layer is then etched to leave exposed only the sidewalls of the stud, at least partially the bottom of the trenches adjacent thereto and the top surface of the stud.

Abstract: The present method discloses the steps to form metal device contact studs between regions of a semiconductor device, such as an NPN vertical bipolar transistor, and the first level metal, the studs overlapping both a contact region (such as the base or the collector) and an adjacent polyimide-filled trench. The method is comprised of the following steps:(a) applying a lift off mask exposing said contact region and adjacent trench without attacking the polyimide fill,(b) blanket depositing the stud forming metal onto the whole structure,(c) lifting off said mask and the overlying metal,(d) blanket depositing a second dielectric layer onto the whole structure, the thickness of said second layer being approximately the stud height,(e) removing said second dielectric layer until the top surface of the highest contact stud is exposed and(f) polishing both the metal and said second dielectric layer to leave a substantially planarized structure ready for further personalization.

Abstract: A process for etching deep trenches to achieve dielectric isolation for integrated circuit devices; the process insures obtaining substantially perfectly vertical trench walls by precluding significant variation in etch bias during the trench formation.

Abstract: A differential reactive ion etching process significantly reduces the reflectivity of silicon. The process takes place in a reactive ion etching tool, typically a diode-configured system employing ambient gases which react with the silicon.