Abstract: In some examples, a network switch includes an Application-Specific Integrated Circuit (ASIC), a processing resource, and a memory resource storing machine readable instructions. The instructions are to cause the processing resource to: accumulate an action set for a first packet received by the switch; fetch an action from the action set; determine, with the ASIC, whether the fetched action is to be performed immediately on the first packet; in response to determining that the fetched action is to be performed immediately, generate a second packet from the first packet; and output one of the first and second packets through an output port without further processing of the packet after generation of the second packet.

Abstract: According to an example, a packet is tunnel encapsulated a packet according to a tunnel encapsulation template. The tunnel encapsulation template includes fields for the tunnel encapsulated packet, and the fields include static fields and variable fields. Field values are inserted into variable fields of the tunnel encapsulation template to generate the tunnel encapsulated packet.

Abstract: In some examples, a network switch includes an Application-Specific Integrated Circuit (ASIC), a processing resource, and a memory resource storing machine readable instructions. The instructions are to cause the processing resource to: accumulate an action set for a first packet received by the switch; fetch an action from the action set; determine, with the ASIC, whether the fetched action is to be performed immediately on the first packet; in response to determining that the fetched action is to be performed immediately, generate a second packet from the first packet; and output one of the first and second packets through an output port without further processing of the packet after generation of the second packet.

Abstract: Examples herein disclose a system including a meter and a networking component. The meter measures a flow rate associated with networking traffic. The networking component identifies a software defined networking (SDN) action path among multiple SDN action paths to perform on the networking traffic based on the measured flow rate.

Abstract: In some examples, a network switch includes an Application-Specific Integrated Circuit (ASIC) including a Network Packet Counter (NPC), a processing resource, and a memory resource storing machine readable instructions. The instructions can, for example, cause the processing resource to assign, in accordance with instructions received by a Software-Defined Network (SDN) controller, a packet flow rule for certain packets received by the network switch to the NPC; modify, with the NPC, a value for a counter associated with the given packet flow rule for received packets that match the pattern of the given packet flow rule; and apply an action to the received packet in accordance with the flow rule only when the value for the counter is less than a threshold value.

Abstract: In some examples, a method includes sending compiled instructions generated from application code to a remote executing unit, the compiled instructions including a particular compiled instruction that maps to a control parameter for the application code. The method may also include receiving a configuration update specifying an updated value for the control parameter, modifying the particular compiled instruction according to the configuration update to obtain a morphed instruction, and sending the morphed instruction to the remote executing unit to replace the particular compiled instruction.

Abstract: According to an example, a packet is tunnel encapsulated a packet according to a tunnel encapsulation template. The tunnel encapsulation template includes fields for the tunnel encapsulated packet, and the fields include static fields and variable fields. Field values are inserted into variable fields of the tunnel encapsulation template to generate the tunnel encapsulated packet.

Abstract: A predicate register is assigned as an exception handling predicate register. An exception may be detected when executing the machine readable instructions. An exception state for the exception is stored in the exception handling predicate register.

Abstract: A network device having a plurality of packet forwarding elements, each including a hardware component for receiving and forwarding data packets from and to other network devices via a plurality of input ports connected to a network. Each hardware component is configured to determine whether a received data packet is one of a predetermined class of data packets based on data in the received data packet and, if so, generate expedited processing instructions corresponding to the received data packet based on data in the received data packet. The hardware component forwards the received data packet, together with the corresponding expedited processing instructions, directly to the hardware component of all packet forwarding elements of the plurality of packet forwarding elements for processing based on the expedited processing instructions.

Abstract: Embodiments herein relate to forwarding an instruction based on predication criteria. A predicate state associated with a packet of data is to be compared to an instruction associated with the predication criteria. The instruction is to be forwarded to an execution unit if the predication criteria includes or matches the predicate state of the packet.

Abstract: Embodiments herein relate to forwarding an instruction based on predication criteria. A predicate state associated with a packet of data is to be compared to an instruction associated with the predication criteria. The instruction is to be forwarded to an execution unit if the predication criteria includes or matches the predicate state of the packet.

Abstract: A network device having a plurality of packet forwarding elements, each including a hardware component for receiving and forwarding data packets from and to other network devices via a plurality of input ports connected to a network. Each hardware component is configured to determine whether a received data packet is one of a predetermined class of data packets based on data in the received data packet and, if so, generate expedited processing instructions corresponding to the received data packet based on data in the received data packet. The hardware component forwards the received data packet, together with the corresponding expedited processing instructions, directly to the hardware component of all packet forwarding elements of the plurality of packet forwarding elements for processing based on the expedited processing instructions.

Abstract: Embodiments herein relate to forwarding an instruction based on predication criteria. A predicate state associated with a packet of data is to be compared to an instruction associated with the predication criteria. The instruction is to be forwarded to an execution unit if the predication criteria includes or matches the predicate state of the packet.

Abstract: The inventive mechanism synthesizes complex software data structures in hardware by using memory transaction translation techniques. The mechanism includes a finite state machine and a bus controller. The state machine has a specific algorithm that defines the dynamic behavior of the synthesized structure. The bus controller manipulates memory control strobes and communicates to the memory bus and bridge. When a transaction references the data structure, the inventive mechanism processes the address of the request into a new address based upon the state of the structure. The finite state machine tracks the current state of the structure and calculates the new state or address. The mechanism the sends out the new address, which is processed by the memory device. The inventive mechanism can also manipulate the read and write aspects to transactions, in addition to the address aspects of the original transaction.

Abstract: A high-performance dual-ported shared memory that interconnects two 32-bit PCI buses with a RAM memory that provides an address space of 64-bit words. The high-performance dual-ported shared memory provides two independent channels for reading from, and writing to, the RAM memory. By interleaving 64-bit read and write operations directed to the RAM memory with 32-bit PCI bus data transfer operations, and by internally buffering data, the high-performance dual-ported shared memory can independently provide data access at PCI data transfer rates to both PCI buses without introducing wait states.

Abstract: The inventive state mechanism assigns N+1 tags to N versions of an object stored in N memory areas. Thus, one tag is unused. An additional tag is used as a null or uninitialized tag. The other tags are assigned in a particular precedence order to revisions as they are stored. Thus, each assigned tag, except the null tag, has both a unique predecessor as well as a unique successor tag. The last tag of the sequence is lower in precedence to the first tag of the sequence, and this forms the cyclic relationship. The unused tag is used to determine the tag that is to be assigned to the next revision. The unused tag is also used to determine which revision is the most current revision. The inventive state mechanism is used by a memory management controller in maintaining the revisions.

Abstract: A high-performance network/bus multiplexer that exchanges data transfer commands and data between different communications mediums, such as the Fibre Channel and one or more SCSI buses. High-performance is achieved by avoiding transmitting read bus operations through bus bridges, and by limiting contention for buses by connecting Fibre Channel host adapters to a first internal bus and SCSI adapters to a second internal bus.

Abstract: There is disclosed a data communications link adapter providing flow of data control and status information between an input/output (I/O) Backplane and a fiber optic Frontplane. The adapter represents a melding of I/O channel extender technology and data communications technology: a dedicated processor handles link layer protocol, leaving to software only higher protocol layers; a flow-through architecture is provided by the adapter; a combination of windowing and handshaking are used; and a relatively short frame of sixteen bytes is employed. The adapter includes a backplane adapter portion which serves to interconnect host equipment, a processor portion dedicated to layer 3 (circuit operations), a protocol controller dedicated to layer 2 (physical layer) operations, a fiber optic interface portion dedicated to layer 1 (physical link) operations, and an arbiter portion which couples the processor to a data path connecting the backplane adapter and the protocol controller.