Abstract: An interface for an ion mobility spectrometry-mass spectrometry (IMS-MS) system includes a first ion guide for receiving ions from an IMS drift cell, and a second ion guide for receiving ions from the first ion guide, and positioned in a chamber separate from the first ion guide. Electrodes of the second ion guide subject the ions to an axial DC electric field while the second ion guide is held at a lower pressure than the first ion guide. In some embodiments, the first ion guide may be an ion funnel and the second ion guide may be a linear multipole device.

Abstract: An ion processing device includes electrically conductive vacuum manifold segments serially positioned and enclosing a volume along an axis. The segments are electrically isolated from each other and independently addressable by a voltage source. An ion optics device is positioned in the volume. A voltage differential between each manifold segment and the ion optics device is maintained below a maximum value by applying different voltages to respective manifold segments. The voltage differential may be controlled to avoid voltage breakdown in a low-pressure, high-voltage gas environment. The ion optics device may in some cases be an ion mobility drift cell.

Abstract: An interface for an ion mobility spectrometry-mass spectrometry (IMS-MS) system includes a first ion guide for receiving ions from an IMS drift cell, and a second ion guide for receiving ions from the first ion guide, and positioned in a chamber separate from the first ion guide. Electrodes of the second ion guide subject the ions to an axial DC electric field while the second ion guide is held at a lower pressure than the first ion guide. In some embodiments, the first ion guide may be an ion funnel and the second ion guide may be a linear multipole device.

Abstract: An ion processing device includes electrically conductive vacuum manifold segments serially positioned and enclosing a volume along an axis. The segments are electrically isolated from each other and independently addressable by a voltage source. An ion optics device is positioned in the volume. A voltage differential between each manifold segment and the ion optics device is maintained below a maximum value by applying different voltages to respective manifold segments. The voltage differential may be controlled to avoid voltage breakdown in a low-pressure, high-voltage gas environment. The ion optics device may in some cases be an ion mobility drift cell.

Abstract: Display contrast in electro-optical display devices is improved using a drive circuit including pixel drive circuits and a common drive circuit. The pixel drive circuits are connected to pixel electrodes of the display device, and are operable to generate respective pixel drive signals that alternate between a first high voltage and a first low voltage differing in voltage by less than or equal to a process-limited maximum. The common drive circuit is connected to a common electrode of the display device, and is operable to generate a common drive signal alternating between a second high voltage and a second low voltage differing in voltage by more than the process-limited maximum. The common drive signal is asymmetrically bipolar with respect to the first low voltage of the pixel drive signal.

Abstract: A frequency detector for use with a PLL utilizes a counter and a preset value to produce frequency information related to a VCO signal. The frequency information is used to control the frequency of the VCO signal and to determine whether the VCO signal should be controlled by the frequency detector or a phase detector. Using the counter and preset value involves establishing a preset value that is used to obtain the desired frequency information. The preset value is set such that the counter is at one-half full-scale at the end of a known time period when the VCO signal is oscillating at a target frequency. When the preset value is set to such a value, the most significant bit of the counter after the known time period indicates whether the frequency of the VCO signal is above or below the target frequency.

Abstract: A technique for reducing the likelihood that a frequency detector will incorrectly assert control over a VCO because of metastable-induced errors involves qualifying frequency detector control signals by requiring multiple consecutive control signals that indicate the frequency detector should assert control over the VCO before the frequency detector is allowed to assert control over the VCO. In an embodiment, the frequency detector control signals are qualified by a series of full-swing library cell flip-flops.

Abstract: In one embodiment a system and method is arranged for bridging the dead-band when asynchronous signals are compared against each other. There is developed a pair of phase related signals from one of the signals, each phase related signal phase shifted from each other, but having the same frequency as the signal from which it was derived. The other frequency signal is compared against each of the phase-related developed signals to generate an error signal which quadrature rotates when the first and second signals are out of frequency with each other. A control signal is generated when the quadrature rotation is outside a certain limit. The error signal is controllably buffered to insure that the error signal only occurs when the frequencies are offset for a selected period of time.

Abstract: In one embodiment a system and method is arranged for bridging the dead-band when asynchronous signals are compared against each other. There is developed a pair of phase related signals from one of the signals, each phase related signal phase shifted from each other, but having the same frequency as the signal from which it was derived. The other frequency signal is compared against each of the phase-related developed signals to generate an error signal which quadrature rotates when the first and second signals are out of frequency with each other. A control signal is generated when the quadrature rotation is outside a certain limit. The error signal is controllably buffered to insure that the error signal only occurs when the frequencies are offset for a selected period of time.

Abstract: An apparatus and a method for protecting charge storage elements from photo-induced currents in silicon integrated circuits are provided. In order to protect against photo-induced currents that are generated outside the storage node circuits themselves, an n-well guard ring is placed as closely as possible to the transistors and other elements in the storage node circuits. As a result there is a minimum of exposed silicon area in which light can produce current in areas next to the storage node circuits, and the n-well guard ring captures photo-induced currents that are generated outside the storage node circuits. In order to protect against the photo-induced currents that are generated inside the storage node circuits, an aluminum interconnect layer is placed on top of the storage node circuit, separated by an insulating layer of silicon dioxide. This creates a shield against the light and protects the storage node circuit by reflecting light away.

Abstract: An apparatus and a method for protecting charge storage elements from photo-induced currents in silicon integrated circuits are provided. In order to protect against photo-induced currents that are generated outside the storage node circuits themselves, an n-well guard ring is placed as closely as possible to the transistors and other elements in the storage node circuits. As a result there is a minimum of exposed silicon area in which light can produce current in areas next to the storage node circuits, and the n-well guard ring captures photo-induced currents that are generated outside the storage node circuits. In order to protect against the photo-induced currents that are generated inside the storage node circuits, an aluminum interconnect layer is placed on top of the storage node circuit, separated by an insulating layer of silicon dioxide. This creates a shield against the light and protects the storage node circuit by reflecting light away.

Abstract: An interleaved, tunable ring oscillator is disclosed that produces more output phases without resorting to interpolation. The oscillator is inherently symmetrical and suffers from none of the systematic time errors of an interpolator approach. The oscillator stages are interconnected to allow the oscillating frequency to be higher than the conventional limit of 1/(2*N*T.sub.D). Frequency tuning is accomplished by electronically varying the delay of each stage of the ring oscillator. A mixer cell performs a weighted sum of a first input and a second delayed input. The delay ranges from the delay of the mixer itself to the sum of the delays of the mixer and the delay cell.

Abstract: A circuit for time stamping event signals, e.g. zero-crossings, using coarse and fine timers. The fine timer is a circuit section which subdivides a period from a phase-locked ring-oscillator into 2N subparts. An event signal is timed by latching a digital representation of a particular subpart. The digital representation of the subpart is an N-bit dual thermometer code which uniquely identifies each subpart with each adjacent subpart differing by only one bit. The subparts are made finer in time quantization than the propagation delay of one active element in the ring oscillator by the use of linear combiner elements. The dual thermometer code, encoded post-latching into a binary code, forms the "fine" timing part of a binary word representation of the event time. The event also latches the count states of a pair of lead-lag counters in a master-slave configuration counting ring oscillator periods. These counters change states respectively before and after the dual thermometer code turn-overs.

Abstract: An integrated circuit package suitable for gigahertz range operation with many power lines is provided with a separate power line structure comprising a uniformly and degenerately doped silicon substrate, a bifurcated thin-film insulator, and area-filling wedge-shaped power lines deposited over the insulator. This arrangement provides a high capacitance distributed right up to the die-interfacing region of the power lines. The effect is to minimize noise that could otherwise be introduced near the die-interfacing region at high frequencies. In addition, the power line structure provides a stable bias at the die-interfacing region of a separate signal line structure for resistive termination of digital signal lines.