Patents by Inventor Thomas A. Letson
Thomas A. Letson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10236356Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.Type: GrantFiled: August 9, 2017Date of Patent: March 19, 2019Assignee: Intel CorporationInventors: Uday Shah, Brian S. Doyle, Justin K. Brask, Robert S. Chau, Thomas A. Letson
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Publication number: 20170365677Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.Type: ApplicationFiled: August 9, 2017Publication date: December 21, 2017Inventors: Uday SHAH, Brian S. DOYLE, Justin K. BRASK, Robert S. CHAU, Thomas A. LETSON
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Patent number: 9741809Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.Type: GrantFiled: September 16, 2015Date of Patent: August 22, 2017Assignee: Intel CorporationInventors: Uday Shah, Brian S. Doyle, Justin K. Brask, Robert S. Chau, Thomas A. Letson
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Publication number: 20160005829Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.Type: ApplicationFiled: September 16, 2015Publication date: January 7, 2016Inventors: Uday Shah, Brian S. Doyle, Justin K. Brask, Robert S. Chau, Thomas A. Letson
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Patent number: 9190518Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.Type: GrantFiled: May 8, 2014Date of Patent: November 17, 2015Assignee: Intel CorporationInventors: Uday Shah, Brian S. Doyle, Justin K. Brask, Robert S. Chau, Thomas A. Letson
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Publication number: 20140239358Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.Type: ApplicationFiled: May 8, 2014Publication date: August 28, 2014Inventors: Uday Shah, Brian S. Doyle, Justin K. Brask, Robert S. Chau, Thomas A. Letson
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Patent number: 8749026Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.Type: GrantFiled: June 3, 2013Date of Patent: June 10, 2014Assignee: Intel CorporationInventors: Uday Shah, Brian S. Doyle, Justin K. Brask, Robert S. Chau, Thomas A. Letson
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Publication number: 20130264642Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.Type: ApplicationFiled: June 3, 2013Publication date: October 10, 2013Inventors: Uday Shah, Brian S. Doyle, Justin K. Brask, Robert S. Chau, Thomas A. Letson
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Patent number: 8502351Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.Type: GrantFiled: September 23, 2011Date of Patent: August 6, 2013Assignee: Intel CorporationInventors: Uday Shah, Brian Doyle, Justin K. Brask, Robert S. Chau, Thomas A. Letson
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Publication number: 20120012934Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.Type: ApplicationFiled: September 23, 2011Publication date: January 19, 2012Inventors: Uday Shah, Brian Doyle, Justin K. Brask, Robert S. Chau, Thomas A. Letson
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Patent number: 8067818Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.Type: GrantFiled: November 24, 2010Date of Patent: November 29, 2011Assignee: Intel CorporationInventors: Uday Shah, Brian Doyle, Justin K. Brask, Robert S. Chau, Thomas A. Letson
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Publication number: 20110062512Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.Type: ApplicationFiled: November 24, 2010Publication date: March 17, 2011Inventors: Uday Shah, Brian Doyle, Justin K. Brask, Robert S. Chau, Thomas A. Letson
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Patent number: 7821044Abstract: Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.Type: GrantFiled: January 15, 2008Date of Patent: October 26, 2010Assignee: Intel CorporationInventors: Mark T. Bohr, Steven J. Keating, Thomas A. Letson, Anand S. Murthy, Donald W. O'Neill, Willy Rachmady
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Patent number: 7550333Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.Type: GrantFiled: May 23, 2006Date of Patent: June 23, 2009Assignee: Intel CorporationInventors: Uday Shah, Brian Doyle, Justin K. Brask, Robert S. Chau, Thomas A. Letson
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Patent number: 7494858Abstract: Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.Type: GrantFiled: June 30, 2005Date of Patent: February 24, 2009Assignee: Intel CorporationInventors: Mark T. Bohr, Steven J. Keating, Thomas A. Letson, Anand S. Murthy, Donald W. O'Neill, Willy Rachmady
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Publication number: 20080135894Abstract: Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.Type: ApplicationFiled: January 15, 2008Publication date: June 12, 2008Inventors: Mark T. Bohr, Steven J. Keating, Thomas A. Letson, Anand S. Murthy, Donald W. O'Neill, Willy Rachmady
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Patent number: 7208399Abstract: A transistor having a gate electrode with a T-shaped cross section is fabricated from a single layer of conductive material using an etching process. A two process etch is performed to form side walls having a notched profile. The notches allow source and drain regions to be implanted in a substrate and thermally processed without creating excessive overlap capacitance with the gate electrode. The reduction of overlap capacitance increases the operating performance of the transistor, including drive current.Type: GrantFiled: July 22, 2004Date of Patent: April 24, 2007Assignee: Intel CorporationInventors: Charles Chu, Thomas A. Letson
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Publication number: 20070004123Abstract: Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.Type: ApplicationFiled: June 30, 2005Publication date: January 4, 2007Inventors: Mark Bohr, Steven Keating, Thomas Letson, Anand Murthy, Donald O'Neill, Willy Rachmady
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Publication number: 20060214231Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.Type: ApplicationFiled: May 23, 2006Publication date: September 28, 2006Inventors: Uday Shah, Brian Doyle, Justin Brask, Robert Chau, Thomas Letson
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Publication number: 20060086977Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.Type: ApplicationFiled: October 25, 2004Publication date: April 27, 2006Inventors: Uday Shah, Brian Doyle, Justin Brask, Robert Chau, Thomas Letson