Patents by Inventor Thomas A. Liebsch
Thomas A. Liebsch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9037892Abstract: An apparatus, method and computer program product for automatically controlling power dissipation of a parallel computing system that includes a plurality of processors. A computing device issues a command to the parallel computing system. A clock pulse-width modulator encodes the command in a system clock signal to be distributed to the plurality of processors. The plurality of processors in the parallel computing system receive the system clock signal including the encoded command, and adjusts power dissipation according to the encoded command.Type: GrantFiled: April 13, 2011Date of Patent: May 19, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul W. Coteus, Alan Gara, Thomas M. Gooding, Rudolf A. Haring, Gerard V. Kopcsay, Thomas A. Liebsch, Don D. Reed
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Patent number: 8595554Abstract: Fixing a problem is usually greatly aided if the problem is reproducible. To ensure reproducibility of a multiprocessor system, the following aspects are proposed: a deterministic system start state, a single system clock, phase alignment of clocks in the system, system-wide synchronization events, reproducible execution of system components, deterministic chip interfaces, zero-impact communication with the system, precise stop of the system and a scan of the system state.Type: GrantFiled: May 5, 2010Date of Patent: November 26, 2013Assignee: International Business Machines CorporationInventors: Ralph A. Bellofatto, Dong Chen, Paul W. Coteus, Noel A. Eisley, Alan Gara, Thomas M. Gooding, Rudolf A. Haring, Philip Heidelberger, Gerard V. Kopcsay, Thomas A. Liebsch, Martin Ohmacht, Don D. Reed, Robert M. Senger, Burkhard Steinmacher-Burow, Yutaka Sugawara
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Patent number: 8412974Abstract: A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.Type: GrantFiled: January 29, 2010Date of Patent: April 2, 2013Assignee: International Business Machines CorporationInventors: Dong Chen, Matthew R. Ellavsky, Ross L. Franke, Alan Gara, Thomas M. Gooding, Rudolf A. Haring, Mark J. Jeanson, Gerard V. Kopcsay, Thomas A. Liebsch, Daniel Littrell, Martin Ohmacht, Don D. Reed, Brandon E. Schenck, Richard A. Swetz
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Publication number: 20120266008Abstract: An apparatus, method and computer program product for automatically controlling power dissipation of a parallel computing system that includes a plurality of processors. A computing device issues a command to the parallel computing system. A clock pulse-width modulator encodes the command in a system clock signal to be distributed to the plurality of processors. The plurality of processors in the parallel computing system receive the system clock signal including the encoded command, and adjusts power dissipation according to the encoded command.Type: ApplicationFiled: April 13, 2011Publication date: October 18, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul W. Coteus, Alan Gara, Thomas M. Gooding, Rudolf A. Haring, Gerard V. Kopcsay, Thomas A. Liebsch, Don D. Reed
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Publication number: 20110119521Abstract: Fixing a problem is usually greatly aided if the problem is reproducible. To ensure reproducibility of a multiprocessor system, the following aspects are proposed: a deterministic system start state, a single system clock, phase alignment of clocks in the system, system-wide synchronization events, reproducible execution of system components, deterministic chip interfaces, zero-impact communication with the system, precise stop of the system and a scan of the system state.Type: ApplicationFiled: May 5, 2010Publication date: May 19, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ralph A. Bellofatto, Dong Chen, Paul W. Coteus, Noel A. Eisley, Alan Gara, Thomas M. Gooding, Rudolf A. Haring, Philip Heidelberger, Gerard V. Kopcsay, Thomas A. Liebsch, Martin Ohmacht, Don D. Reed, Robert M. Senger, Burkhard Steinmacher-Burow, Yutaka Sugawara
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Publication number: 20110119475Abstract: A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.Type: ApplicationFiled: January 29, 2010Publication date: May 19, 2011Applicant: International Business Machines CorporationInventors: Dong Chen, Matthew R. Ellavsky, Ross L. Franke, Alan Gara, Thomas M. Gooding, Rudolf A. Haring, Mark J. Jeanson, Gerard V. Kopcsay, Thomas A. Liebsch, Daniel Littrell, Martin Ohmacht, Don D. Reed, Brandon E. Schenck, Richard A. Swetz
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Patent number: 7941681Abstract: Proactive power management in a parallel computer, the parallel computer including a service node and a plurality of compute nodes, the service node connected to the compute nodes through an out-of-band service network, each compute node including a computer processor and a computer memory operatively coupled to the computer processor. Embodiments include receiving, by the service node, a user instruction to initiate a job on an operational group of compute nodes in the parallel computer, the instruction including power management attributes for the compute nodes; setting, by the service node in accordance with the power management attributes for the compute nodes of the operational group, power consumption ratios for each compute node of the operational group including a computer processor power consumption ratio and a computer memory power consumption ratio; and initiating, by the service node, the job on the compute nodes of the operational group of the parallel computer.Type: GrantFiled: August 17, 2007Date of Patent: May 10, 2011Assignee: International Business Machines CorporationInventors: Thomas M. Gooding, Todd A. Inglett, Thomas A. Liebsch, Thomas E. Musta, Don D. Reed
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Patent number: 7877620Abstract: Managing power in a parallel computer, the parallel computer including a power supply and a plurality of compute nodes, the plurality of compute nodes powered by the power supply through a plurality of DC-DC converters, each DC-DC converter supplying current to an assigned group of compute nodes, each DC-DC converter having a current sensor. Embodiments include monitoring, by the current sensor, an amount of current supplied by that DC-DC converter to its assigned group of compute nodes; determining, by at least one DC-DC converter, that the amount of current supplied is greater than a predefined threshold value; sending, by the at least one DC-DC converter to the plurality of compute nodes, a global interrupt, including notifying the plurality of compute nodes to reduce power consumption; and reducing, by the plurality of compute nodes in accordance with power consumption ratios, power consumption of the compute nodes.Type: GrantFiled: August 17, 2007Date of Patent: January 25, 2011Assignee: International Business Machines CorporationInventors: Alan Gara, Thomas M. Gooding, Todd A. Inglett, Thomas A. Liebsch, Thomas E. Musta
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Publication number: 20090049317Abstract: Managing power in a parallel computer, the parallel computer including a power supply and a plurality of compute nodes, the plurality of compute nodes powered by the power supply through a plurality of DC-DC converters, each DC-DC converter supplying current to an assigned group of compute nodes, each DC-DC converter having a current sensor. Embodiments include monitoring, by the current sensor, an amount of current supplied by that DC-DC converter to its assigned group of compute nodes; determining, by at least one DC-DC converter, that the amount of current supplied is greater than a predefined threshold value; sending, by the at least one DC-DC converter to the plurality of compute nodes, a global interrupt, including notifying the plurality of compute nodes to reduce power consumption; and reducing, by the plurality of compute nodes in accordance with power consumption ratios, power consumption of the compute nodes.Type: ApplicationFiled: August 17, 2007Publication date: February 19, 2009Inventors: Alan Gara, Thomas M. Gooding, Todd A. Inglett, Thomas A. Liebsch, Thomas E. Musta
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Publication number: 20090049313Abstract: Proactive power management in a parallel computer, the parallel computer including a service node and a plurality of compute nodes, the service node connected to the compute nodes through an out-of-band service network, each compute node including a computer processor and a computer memory operatively coupled to the computer processor. Embodiments include receiving, by the service node, a user instruction to initiate a job on an operational group of compute nodes in the parallel computer, the instruction including power management attributes for the compute nodes; setting, by the service node in accordance with the power management attributes for the compute nodes of the operational group, power consumption ratios for each compute node of the operational group including a computer processor power consumption ratio and a computer memory power consumption ratio; and initiating, by the service node, the job on the compute nodes of the operational group of the parallel computer.Type: ApplicationFiled: August 17, 2007Publication date: February 19, 2009Inventors: Thomas M Gooding, Todd A. Inglett, Thomas A. Liebsch, Thomas E. Musta, Don D. Reed
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Publication number: 20070168695Abstract: A method and apparatus for re-utilizing partially failed compute resources in a massively parallel super computer system. In the preferred embodiments the compute node comprises a number of clock domains that can be enabled separately. When an error in a compute node is detected, and the failure is not in network communication blocks, a clock enable circuit enables the clocks to the network communication blocks only to allow the partially failed compute node to be re-utilized as a network resource. The computer system can then continue to operate with only slightly diminished performance and thereby improve performance and perceived overall reliability.Type: ApplicationFiled: January 19, 2006Publication date: July 19, 2007Applicant: International Business Machines CorporationInventors: Dong Chen, Alan Gara, Philip Heidelberger, Thomas Liebsch, Burkhard Steinmacher-Burow, Pavlos Vranas