Abstract: A special instruction processor that connects to a central processing unit in a data processing system. The central processing unit processes a number of instructions. Instructions involving operands first retrieve the operands from memory, from general purpose registers in the central processor or the instruction stream. These operands are transferred to the special instruction processor. If the instruction is one of a predetermined set of instructions that is executed by the special instruction processor, the special instruction processor will, upon receiving the operands, generate an overriding signal that alters the operation of the central processor unit by inhibiting its processing of the operands. Instead, the special instruction processor unit, that is specifically designed to perform the operations efficiently, computes a result.

Abstract: A random access memory module for connection in a memory arrangement for a digital data processing system that additionally includes a high speed associative memory unit. The associative memory unit contains a multiple location address memory and a multiple location data memory wherein there is a correspondence between each address location and a data location. Each time a central processor in the system initiates a reading operation, it issues an address to define a data location. If the associative memory unit contains that address at a location in its address memory, it performs a reading memory cycle and transfers data from the corresponding location in the data memory directly to the central processor. On the other hand, if the associative memory does not contain that address, it initiates a reading memory cycle with the random access memory module.

Abstract: A secondary storage facility that connects to a digital data processing system. The system includes a central processor, an associative memory and a random access memory connected to the associative memory. The secondary storage facility includes a controller and one or more direct access secondary storage units. A first bus connector interconnects the controller to a first bus from the central processor and transfers of control information are routed over this bus. The controller also connects to the associative memory so that data, together with address and control information, is routed between the random access memory and a storage unit through this second connection.

Abstract: A memory arrangement for a digital data processing system that includes a high-speed associative memory unit and a random access back-up unit. The associative memory unit contains a multiple location address memory and a multiple location data memory wherein there is a correspondence between each address location and a data location. Each time a central processor initiates a reading operation, it issues an address to define a data location. If the associative memory unit contains that address at a location in its address memory, it performs a reading memory cycle and transfers data from the corresponding location in the data memory directly to the central processor. If the data is not available in the associative memory unit during a reading operation, or if the central processor is transferring data to the address location during a writing operation, the associative memory unit causes the back-up unit to perform a corresponding memory cycle.