Patents by Inventor Thomas A. Rampone

Thomas A. Rampone has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6020751
    Abstract: A method and apparatus for testing a circuit board is disclosed. An apparatus having at least one clock source for providing a circuit board with a clock signal at a dynamically selected frequency, a storage medium storing programming instructions to control the clock source(s) to provide the clock signal at the dynamically selected frequency including a frequency that exceeds the specified operating range of frequencies for the circuit board, and for implementing parametric testing of the circuit board, and an execution unit coupled to the clock source and to the storage medium for executing the programming instructions. The programming instructions for implementing the parametric testing of the circuit board include instructions for testing the circuit board while the circuit board is supplied with the clock signal at the frequency that exceeds the operating frequency of the circuit board, thereby stressing the circuit board.
    Type: Grant
    Filed: January 2, 1997
    Date of Patent: February 1, 2000
    Assignee: Intel Corporation
    Inventors: Thomas A. Rampone, Jerald N. Hall
  • Patent number: 5966020
    Abstract: A split-pad land pattern configured to facilitate electrical testing of an interconnection between a single electrical contact of a surface mount technology component and a printed circuit board. The split-pad land pattern comprises at least one split mounting pad including at least a first and second mounting pads coupled to a single electrical contact. The mounting pads are further coupled to corresponding access pads so that a first access pad is coupled to the first mounting pad while a second access pad is coupled to the second mounting pad. Electrical testing of the single electrical contact is possible through the completed circuit between the two access pads.
    Type: Grant
    Filed: October 30, 1996
    Date of Patent: October 12, 1999
    Assignee: Intel Corporation
    Inventors: Thomas Rampone, George Arrigotti
  • Patent number: 5939868
    Abstract: A method and apparatus for automatically controlling integrated circuit supply voltages includes, according to one embodiment, a primary voltage regulator and a secondary voltage regulator. The primary voltage regulator supplies one of either a first voltage or a second voltage to a first plurality of inputs of an integrated circuit. The secondary voltage regulator conditionally supplies a third voltage to a second plurality of inputs of the integrated circuit in the event the primary voltage regulator supplies the first voltage, with the third voltage being substantially the same as the second voltage.
    Type: Grant
    Filed: July 13, 1998
    Date of Patent: August 17, 1999
    Assignee: Intel Corporation
    Inventors: Jerald Nevin Hall, Thomas A. Rampone, Kirk Tyler Byers
  • Patent number: 5787014
    Abstract: A method and apparatus for automatically controlling integrated circuit supply voltages includes, according to one embodiment, a primary voltage regulator and a secondary voltage regulator. The primary voltage regulator supplies one of either a first voltage or a second voltage to a first plurality of inputs of an integrated circuit. The secondary voltage regulator conditionally supplies a third voltage to a second plurality of inputs of the integrated circuit in the event the primary voltage regulator supplies the first voltage, with the third voltage being substantially the same as the second voltage.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: July 28, 1998
    Assignee: Intel Corporation
    Inventors: Jerald Nevin Hall, Thomas A. Rampone, Kirk Tyler Byers
  • Patent number: 5638529
    Abstract: An apparatus is provided for controlling a memory refresh operation in a computer system having a processor coupled to a host volatile memory via a memory controller, a system bus controller coupled to the processor via the memory controller, and a plurality of devices coupled to the system bus controller via a system bus. The apparatus includes a first timer coupled to the memory controller for generating a first memory refresh signal at a first predetermined time interval to cause the memory controller to perform the memory refresh operation on the host volatile memory. A second timer is coupled to the system bus controller for generating a second memory refresh signal at a selective time interval to causes the system bus controller to perform the memory refresh operation on the plurality of devices. A program is provided for detecting the refresh requirement of the plurality of devices in order to determine the selective time interval.
    Type: Grant
    Filed: February 17, 1995
    Date of Patent: June 10, 1997
    Assignee: Intel Corporation
    Inventors: Dawson L. Yee, Thomas A. Rampone