Abstract: Software simulators of logic design circuits run slowly but are capable of providing very finely detailed error trace analyses. On the other hand, hardware accelerators operating to perform similar functions are very fast in their execution but are not capable of practically isolating error states or other critical conditions. Accordingly, the present invention provides an interactive system combining software simulators and hardware accelerators so that when desired test results do not favorably compare with simulated results, a mechanism is provided for storing the current hardware accelerator state and restoring the accelerator to a previous checkpoint state which has been saved as a result of a prior periodic interruption. The hardware accelerator is then operated for a time sufficient to bring it up to a state that occurs just before the detected miscomparison. At this point, state information from the hardware accelerator is supplied to a software simulator for detailed error analysis and fault tracing.

Abstract: This mechanism preserves the identity of the first error condition which is capable of causing a machine check even though other such conditions may have occurred before the data processing machine has stopped. After the first machine check condition has been examined, the remaining conditions, if any, will be examined in accordance with a predetermined priority irrespective of the time sequence in which they occur.

Abstract: A mechanism is provided for saving substantial time when a service processor needs to communicate with one of a plurality of satellite devices, but does not know the identity of the specific device. The service processor, through an intermediate adapter, issues a command which addresses the class of devices. The adapter redirects the command to the specific device, and concatenates the response from that device along with the device's identity and forwards this to the service processor. Further communication between the service processor and the specific device can then take place directly.

Abstract: In a multiprocessor system which includes a plurality of service processors, only one of the service processors is actively in control of the system, while the other is a backup. Upon the occurrence of a malfunction in the active service processor, the standby service processor can be switched in to assume control of the system. The service processor which had been active then becomes the backup system.