Patents by Inventor Thomas A. Tetzlaff
Thomas A. Tetzlaff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12382307Abstract: Logic may enable client devices or access points to relay medium access control (MAC) frames through a Wireless Fidelity (Wi-Fi) Direct network such as a network of Peer-to-Peer (P2P) connections to extend the wireless range of the devices or access points beyond the transmission range of the individual devices or access points. Logic may extend the range of IEEE 802.11 devices, such as IEEE 802.11ah devices, by allowing a station in the middle of two stations to serve as a relay station using the Wi-Fi Direct technology. Logic may enable relaying to avoid a full mesh technology such as is defined in IEEE 802.11s, since the full mesh technology may contain too many features that are not required for a simple or a static network configuration of such embodiments.Type: GrantFiled: January 5, 2023Date of Patent: August 5, 2025Assignee: Intel CorporationInventors: Minyoung Park, Emily H. Qi, Adrian P. Stephens, Thomas J. Kenney, Eldad Perahia, Thomas A. Tetzlaff
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Publication number: 20240272933Abstract: Embodiments described herein provide a system, method, and apparatus to accelerate reduce operations in a graphics processor. One embodiment provides an apparatus including one or more processors, the one or more processors including a first logic unit to perform a merged write, barrier, and read operation in response to a barrier synchronization request from a set of threads in a work group, synchronize the set of threads, and broadcast a result of an operation specified in association with the barrier synchronization request.Type: ApplicationFiled: April 4, 2024Publication date: August 15, 2024Applicant: Intel CorporationInventors: Yong Jiang, Yuanyuan Li, Jianghong Du, Kuilin Chen, Thomas A. Tetzlaff
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Patent number: 11989580Abstract: Embodiments described herein provide a system, method, and apparatus to accelerate reduce operations in a graphics processor. One embodiment provides an apparatus including one or more processors, the one or more processors including a first logic unit to perform a merged write, barrier, and read operation in response to a barrier synchronization request from a set of threads in a work group, synchronize the set of threads, and report a result of an operation specified in association with the barrier synchronization request.Type: GrantFiled: March 10, 2021Date of Patent: May 21, 2024Assignee: Intel CorporationInventors: Yong Jiang, Yuanyuan Li, Jianghong Du, Kuilin Chen, Thomas A. Tetzlaff
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Publication number: 20230224724Abstract: Logic may enable client devices or access points to relay medium access control (MAC) frames through a Wireless Fidelity (Wi-Fi) Direct network such as a network of Peer-to-Peer (P2P) connections to extend the wireless range of the devices or access points beyond the transmission range of the individual devices or access points. Logic may extend the range of IEEE 802.11 devices, such as IEEE 802.11ah devices, by allowing a station in the middle of two stations to serve as a relay station using the Wi-Fi Direct technology. Logic may enable relaying to avoid a full mesh technology such as is defined in IEEE 802.11s, since the full mesh technology may contain too many features that are not required for a simple or a static network configuration of such embodiments.Type: ApplicationFiled: January 5, 2023Publication date: July 13, 2023Applicant: Intel CorporationInventors: Minyoung Park, Emily H. Qi, Adrian P. Stephens, Thomas J. Kenney, Eldad Perahia, Thomas A. Tetzlaff
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Patent number: 11582617Abstract: Logic may enable client devices or access points to relay medium access control (MAC) frames. Logic may extend the range of IEEE 802.11 devices, such as IEEE 802.11ah devices.Type: GrantFiled: August 7, 2017Date of Patent: February 14, 2023Assignee: Intel CorporationInventors: Minyoung Park, Emily H. Qi, Adrian P. Stephens, Thomas J. Kenney, Eldad Perahia, Thomas A. Tetzlaff
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Publication number: 20210334127Abstract: Embodiments described herein provide a system, method, and apparatus to accelerate reduce operations in a graphics processor. One embodiment provides an apparatus including one or more processors, the one or more processors including a first logic unit to perform a merged write, barrier, and read operation in response to a barrier synchronization request from a set of threads in a work group, synchronize the set of threads, and report a result of an operation specified in association with the barrier synchronization request.Type: ApplicationFiled: March 10, 2021Publication date: October 28, 2021Applicant: Intel CorporationInventors: Yong JIANG, Yuanyuan Li, Jianghong Du, Kuilin Chen, Thomas A. Tetzlaff
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Patent number: 10949251Abstract: Embodiments described herein provide a system, method, and apparatus to accelerate reduce operations in a graphics processor. One embodiment provides an apparatus including one or more processors, the one or more processors including a first logic unit to perform a merged write, barrier, and read operation in response to a barrier synchronization request from a set of threads in a work group, synchronize the set of threads, and report a result of an operation specified in association with the barrier synchronization request.Type: GrantFiled: April 1, 2016Date of Patent: March 16, 2021Assignee: INTEL CORPORATIONInventors: Yong Jiang, Yuanyuan Li, Jianghong Du, Kuilin Chen, Thomas A. Tetzlaff
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Patent number: 10680749Abstract: A decoder having an input configured to receive a sequence of softbits presumed to correspond to a convolutionally-encoded codeword; and a decoding circuit configured to: determine, as part of a decoding process, a Maximum Likelihood (ML) survivor path in a trellis representation of the codeword; determine whether the presumed convolutionally-encoded codeword meets an early-termination criteria; and abort the decoding process if the presumed convolutionally-encoded codeword meets the early-termination criteria, continue the decoding process if the presumed convolutionally-encoded codeword fails to meet the early-termination criteria.Type: GrantFiled: July 1, 2017Date of Patent: June 9, 2020Assignee: Intel CorporationInventors: David Arditti Ilitzky, Thomas A. Tetzlaff
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Patent number: 10349405Abstract: Logic may coordinate communications of different types of wireless communications devices such as high power and low power wireless communications devices. Logic may coordinate communications by assigning time slots to a low power station (LP-STA) in a management frame such as a beacon transmitted by an access point (AP) associated with the LP-STA. Logic of the high power stations (HP-STAs) may receive the beacon and shepard logic of the HP-STA may defer transmissions by the HP-STA throughout the duration(s) indicated in the beacon from the AP. Logic of the LP-STA may comprise carrier sense multiple access with collision avoidance logic to determine when to transmit a communication. Shepard logic of an HP-STA may detect the communication from the LP-STA and defer transmission of communication during a time duration for the communication by the LP-STA.Type: GrantFiled: March 21, 2018Date of Patent: July 9, 2019Assignee: Intel CorporationInventors: Minyoung Park, Adrian P. Stephens, Emily H. Qi, Thomas A. Tetzlaff
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Publication number: 20190026149Abstract: Embodiments described herein provide a system, method, and apparatus to accelerate reduce operations in a graphics processor. One embodiment provides an apparatus including one or more processors, the one or more processors including a first logic unit to perform a merged write, barrier, and read operation in response to a barrier synchronization request from a set of threads in a work group, synchronize the set of threads, and report a result of an operation specified in association with the barrier synchronization request.Type: ApplicationFiled: April 1, 2016Publication date: January 24, 2019Inventors: Yong JIANG, Yuanyuan LI, Jianghong DU, Kuilin CHEN, Thomas A. TETZLAFF
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Publication number: 20190007068Abstract: A decoder having an input configured to receive a sequence of softbits presumed to correspond to a convolutionally-encoded codeword; and a decoding circuit configured to: determine, as part of a decoding process, a Maximum Likelihood (ML) survivor path in a trellis representation of the codeword; determine whether the presumed convolutionally-encoded codeword meets an early-termination criteria; and abort the decoding process if the presumed convolutionally-encoded codeword meets the early-termination criteria, continue the decoding process if the presumed convolutionally-encoded codeword fails to meet the early-termination criteria.Type: ApplicationFiled: July 1, 2017Publication date: January 3, 2019Inventors: David Arditti Ilitzky, Thomas A. Tetzlaff
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Publication number: 20180317224Abstract: Logic may coordinate communications of different types of wireless communications devices such as high power and low power wireless communications devices. Logic may coordinate communications by assigning time slots to a low power station (LP-STA) in a management frame such as a beacon transmitted by an access point (AP) associated with the LP-STA. Logic of the high power stations (HP-STAs) may receive the beacon and shepard logic of the HP-STA may defer transmissions by the HP-STA throughout the duration(s) indicated in the beacon from the AP. Logic of the LP-STA may comprise carrier sense multiple access with collision avoidance logic to determine when to transmit a communication. Shepard logic of an HP-STA may detect the communication from the LP-STA and defer transmission of communication during a time duration for the communication by the LP-STA.Type: ApplicationFiled: March 21, 2018Publication date: November 1, 2018Inventors: Minyoung Park, Adrian P. Stephens, Emily H. Qi, Thomas A. Tetzlaff
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Patent number: 9980168Abstract: This application discusses apparatus and methods of saving power using a quadrature receiver by enabling a single string reception mode of the quadrature receiver. In an example, a receiver for receiving communication information can include an analog front end configured to receive a modulated, information-carrying radio frequency signal at a first frequency band and to provide a digital representation of the modulated, information-carrying radio frequency signal at a second frequency band, a digital front end configured to receive the digital representation at the second frequency and to provide the communication information, for example, to a baseband processor. In a first processing mode of the receiver, the analog front end can provide either one of in-phase symbol information of the modulated, information-carrying radio frequency signal or quadrature symbol information of the modulated, information-carrying radio frequency signal at the second frequency band.Type: GrantFiled: June 25, 2015Date of Patent: May 22, 2018Assignee: Intel CorporationInventors: David Arditti Ilitzky, Thomas A. Tetzlaff, Edgar Borrayo, Stefano Pellerano
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Publication number: 20180098229Abstract: Logic may enable client devices or access points to relay medium access control (MAC) frames. Logic may extend the range of IEEE 802.11 devices, such as IEEE 802.11ah devices.Type: ApplicationFiled: August 7, 2017Publication date: April 5, 2018Applicant: Intel CorporationInventors: Minyoung Park, Emily H. Qi, Adrian P. Stephens, Thomas J. Kenney, Eldad Perahia, Thomas A. Tetzlaff
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Patent number: 9930661Abstract: Logic may coordinate communications of different types of wireless communications devices such as high power and low power wireless communications devices. Logic may coordinate communications by assigning time slots to a low power station (LP-STA) in a management frame such as a beacon transmitted by an access point (AP) associated with the LP-STA. Logic of the high power stations (HP-STAB) may receive the beacon and shepard logic of the HP-STA may defer transmissions by the HP-STA throughout the duration(s) indicated in the beacon from the AP. Logic of the LP-STA may comprise carrier sense multiple access with collision avoidance logic to determine when to transmit a communication. Shepard logic of an HP-STA may detect the communication from the LP-STA and defer transmission of communication during a time duration for the communication by the LP-STA.Type: GrantFiled: April 18, 2016Date of Patent: March 27, 2018Assignee: Intel CorporationInventors: Minyoung Park, Adrian P. Stephens, Emily H. Qi, Thomas A. Tetzlaff
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Patent number: 9888407Abstract: Embodiments may implement a new hierarchical data structure for traffic indication mapping to facilitate transmissions for wireless communications devices. Many embodiments comprise MAC sublayer logic to generate and transmit management frames such as beacon frames with a partial virtual bitmap based upon the hierarchical data structure for traffic indication mapping. In some embodiments, the MAC sublayer logic may store the traffic indication map and/or the traffic indication map structure in memory, in logic, or in another manner that facilitates transmission of the frames. Some embodiments may receive, detect, and decode communications with frames comprising the partial virtual bitmap based upon the hierarchical data structure. In some embodiments, indications of buffered data for pages, blocks, sub-blocks, and/or stations may be inverted. In several embodiments, a new association identifier (AID) structure is defined for the new hierarchical data structure for traffic indication mapping.Type: GrantFiled: December 31, 2011Date of Patent: February 6, 2018Assignee: Intel CorporationInventors: Minyoung Park, Thomas J. Kenney, Emily H. Qi, Thomas A. Tetzlaff
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Patent number: 9730102Abstract: Logic may compress wireless communications frames and communicate compressed frames that do not include the duplicative bit sequences within the packet flow. Logic may include the compressed frames in flow frames. Logic may generate, encode, transmit, decode, parse, and interpret flow frames after a packet flow is created. Flow frames may comprise a flow frame control field, a compressed frame, and a frame sequence check. Logic may decompress the compressed flow frame based upon flow decompression rules associated with a flow index of the flow frame. Flow frames may include a duration field to set the network allocation vectors of other stations. And the frame sequence check may be generated based upon the entire flow frame.Type: GrantFiled: December 29, 2012Date of Patent: August 8, 2017Assignee: Intel CorporationInventor: Thomas A. Tetzlaff
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Patent number: 9730082Abstract: Logic may enable client devices or access points to relay medium access control (MAC) frames through a Wireless Fidelity (Wi-Fi) Direct network such as a network of Peer-to-Peer (P2P) connections to extend the wireless range of the devices or access points beyond the transmission range of the individual devices or access points. Logic may extend the range of IEEE 802.11 devices, such as IEEE 802.11ah devices, by allowing a station in the middle of two stations to serve as a relay station using the Wi-Fi Direct technology. Logic may enable relaying to avoid a full mesh technology such as is defined in IEEE 802.11s, since the full mesh technology may contain too many features that are not required for a simple or a static network configuration of such embodiments.Type: GrantFiled: December 29, 2012Date of Patent: August 8, 2017Assignee: Intel CorporationInventors: Minyoung Park, Emily H Qi, Adrian P Stephens, Thomas J. Kenney, Eldad Perahia, Thomas A. Tetzlaff
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Publication number: 20160381643Abstract: This application discusses apparatus and methods of saving power using a quadrature receiver by enabling a single string reception mode of the quadrature receiver. In an example, a receiver for receiving communication information can include an analog front end configured to receive a modulated, information-carrying radio frequency signal at a first frequency band and to provide a digital representation of the modulated, information-carrying radio frequency signal at a second frequency band, a digital front end configured to receive the digital representation at the second frequency and to provide the communication information, for example, to a baseband processor. In a first processing mode of the receiver, the analog front end can provide either one of in-phase symbol information of the modulated, information-carrying radio frequency signal or quadrature symbol information of the modulated, information-carrying radio frequency signal at the second frequency band.Type: ApplicationFiled: June 25, 2015Publication date: December 29, 2016Inventors: David Arditti Ilitzky, Thomas A. Tetzlaff, Edgar Borrayo, Stefano Pellerano
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Patent number: 9526029Abstract: Logic may compress wireless communications frames and communicate compressed frames that do not include the duplicative bit sequences within the packet flow. Logic may include the compressed frames in flow frames. Logic may generate, encode, transmit, decode, parse, and interpret flow frames after a packet flow is created. Flow frames may comprise a flow frame control field, a compressed frame, and a frame sequence check. Logic may decompress the compressed flow frame based upon flow decompression rules associated with a flow index of the flow frame. Flow frames may include a duration field to set the network allocation vectors of other stations. And the frame sequence check may be generated based upon the entire flow frame.Type: GrantFiled: December 27, 2014Date of Patent: December 20, 2016Assignee: Intel CorporationInventor: Thomas A. Tetzlaff