Abstract: An oscillator having an adjustable gain circuit provides abundant gain when the oscillator is first powered up but reduces the gain substantially below its start-up value once oscillations build up, thereby substantially reducing the power consumed. The oscillator comprises an inverting amplifier coupled to a resonator, an oscillation detector coupled to the inverting amplifier amplifier, and a common-gate amplifier coupled to the oscillation detector. The inverting amplifier amplifies oscillations of the resonator according to a gain. The oscillation detector outputs a detection signal in response to oscillations of the resonator. The level of the detection signal is proportional to the amplitude of the oscillations. The common-gate amplifier receives the detection signal and, in response, limits the current to the inverting amplifier to control the gain based on the level of the detection signal.

Abstract: An oscillator having an adjustable output frequency comprises a resonator, an inverting amplifier coupled to the resonator, a variable capacitance coupled to the resonator and to the amplifier, and a shift register coupled to the variable capacitance. The variable capacitance comprises a first bank of switchable capacitors coupled to an input of the oscillator and a second bank of switchable capacitors coupled to an output of the oscillator. The shift register includes a plurality of bits and is configured such that the logic state of each bit determines the switching state of a corresponding capacitor from each bank of switchable capacitors. By shifting the bits in the shift register, the variable capacitance is varied, causing an adjustment in the output frequency of the oscillator.