Abstract: An acoustic wave resonator has a first conductive layer, piezoelectrical material formed over the first conductive layer, and second conductive layer formed over the piezoelectric material. An alignment of the first conductive layer, piezoelectric material and second conductive area defines an active region of the resonator and the active region includes a core area and a plurality of fractals extending from or recessed into the core area. The fractals maximize a perimeter-to-area ratio of the active region of the resonator. The fractals increase electromechanical coupling and a quality factor of the resonator. The fractals can have a star shape, rounded shape, asymmetric shape, or other shape that optimizes the perimeter-to-area ratio of the active region to maximize performance of the resonator. A frame can be disposed over or within the piezoelectric material. The frame is raised above the second conductive layer or recessed below the second conductive layer.

Abstract: An acoustic wave resonator has a first conductive layer, piezoelectrical material formed over the first conductive layer, and second conductive layer formed over the piezoelectric material. An alignment of the first conductive layer, piezoelectric material and second conductive area defines an active region of the resonator and the active region includes a core area and a plurality of fractals extending from or recessed into the core area. The fractals maximize a perimeter-to-area ratio of the active region of the resonator. The fractals increase electromechanical coupling and a quality factor of the resonator. The fractals can have a star shape, rounded shape, asymmetric shape, or other shape that optimizes the perimeter-to-area ratio of the active region to maximize performance of the resonator. A frame can be disposed over or within the piezoelectric material. The frame is raised above the second conductive layer or recessed below the second conductive layer.

Abstract: A monolithic microwave integrated circuit (MMIC) compatible broadside-coupled transformer including (i) a first transmission line, (ii) a second transmission line, and (iii) a third transmission line. The first and the second transmission lines generally form the broadside-coupled transformer. The third transmission line is generally connected in series with the broadside-coupled transmission line forming a ground return path of the broadside-coupled transformer.

Abstract: An amplifier output impedance matching configuration including a first impedance transformer and one or more second impedance transformers. The first impedance transformer receives input signals from a power amplifier and generates output signals to a load. The one or more second impedance transformers are connected between the first impedance transformer and the load through which the output signals are passed.

Abstract: A monolithic microwave integrated circuit (MMIC) compatible broadside-coupled transformer including (i) a first transmission line, (ii) a second transmission line, and (iii) a third transmission line. The first and the second transmission lines generally form the broadside-coupled transformer. The third transmission line is generally connected in series with the broadside-coupled transmission line forming a ground return path of the broadside-coupled transformer.

Abstract: An amplifier output impedance matching configuration including a first impedance transformer and one or more second impedance transformers. The first impedance transformer receives input signals from a power amplifier and generates output signals to a load. The one or more second impedance transformers are connected between the first impedance transformer and the load through which the output signals are passed.

Abstract: A Field-Effect Transistor (FET) is provided that includes a first portion and a second portion separated from the first portion by a gap. The FET further includes at least one diode embedded within the gap between the first and second portions. A plurality of FETs also may be provided with adjacent FETs electrically isolated.

Abstract: A MESFET and method for fabricating a MESFET are provided. The method includes forming an n-type channel portion in a substrate and forming a p-type channel portion in the substrate. A boundary of the n-type channel portion and a boundary of the p-type channel portion define an intrinsic region in the substrate.

Abstract: A Field-Effect Transistor (FET) is provided that includes a first portion and a second portion separated from the first portion by a gap. The FET further includes at least one diode embedded within the gap between the first and second portions.

Abstract: HBTs in an HBT array are configured non-linearly, i.e., staggered, thus reducing the impact of thermal coupling between adjacent HBTs in the array and bypassing the minimum collector-to-collector spacing design rules required for a linear HBT array. Using this non-linear configuration, adjacent HBTs are misaligned with respect to each other. In a preferred embodiment, adjacent HBTs in the array are configured in a corner-to-corner arrangement, and in a more preferred embodiment, the collectors of the adjacent HBTs are aligned or are common, i.e., the collector of one HBT is shared with the collector of an adjacent HBT. In a most preferred embodiment, the HBTs are ballasted in an emitter-ballast/base-ballast pattern (referred to as “mixed ballasting” or “dual-ballasting”).

Abstract: The invention is a dual band power amplifier with a small footprint having excellent band-to-band isolation. An improved second and fourth harmonic trap at the output of the low band power amplifier comprises a first capacitance shunted to ground placed in series with an inductance, the inductance preferably in the form of a transmission line of predetermined length, and a second capacitance coupled between an intermediate point of the transmission line inductance and ground. Band-to-band isolation can be additively increased by further forming a ground loop between the outputs of the two power amplifiers. The ground loop further isolates the high band amplifier from the low band amplifier by causing the magnetic fields generated around the output wire bonds of the low band power amplifier to set up circulating currents primarily in the ground loop, rather than coupling into the output wire bonds of the high band power amplifier.

Abstract: The invention is a dual band power amplifier with a small footprint having excellent band-to-band isolation. An improved second and fourth harmonic trap at the output of the low band power amplifier comprises a first capacitance shunted to ground placed in series with an inductance, the inductance preferably in the form of a transmission line of predetermined length, and a second capacitance coupled between an intermediate point of the transmission line inductance and ground. Band-to-band isolation can be additively increased by further forming a ground loop between the outputs of the two power amplifiers. The ground loop further isolates the high band amplifier from the low band amplifier by causing the magnetic fields generated around the output wire bonds of the low band power amplifier to set up circulating currents primarily in the ground loop, rather than coupling into the output wire bonds of the high band power amplifier.

Abstract: HBTs in an HBT array are configured non-linearly, i.e., staggered, thus reducing the impact of thermal coupling between adjacent HBTs in the array and bypassing the minimum collector-to-collector spacing design rules required for a linear HBT array. Using this non-linear configuration, adjacent HBTs are misaligned with respect to each other. In a preferred embodiment, adjacent HBTs in the array are configured in a corner-to-corner arrangement, and in a more preferred embodiment, the collectors of the adjacent HBTs are aligned or are common, i.e., the collector of one HBT is shared with the collector of an adjacent HBT. In a most preferred embodiment, the HBTs are ballasted in an emitter-ballast/base-ballast pattern (referred to as “mixed ballasting” or “dual-ballasting”).

Abstract: The invention features an improved semiconductor device comprising both active and passive devices and a method of manufacturing such semiconductor devices. A method in accord with the invention includes performing front side processing on a front side of the substrate to form an active semiconductor device on the front side of the substrate and performing back side processing on the back side of the substrate. The back side processing includes forming a via through the back side of the substrate to an electrically conductive layer formed on the front side of the substrate and forming a conductive layer in the via to form an electrically conductive path from the back side of the substrate to the electrically conductive layer formed on the front side of the substrate.