Abstract: Structures for fuses to control repair of multiple memories embedded on an integrated circuit are provided along with methods of use. A set of fuses is shared to control repair of a plurality of memories. Some of the fuses are associated with a memory to be repaired. Others of the fuses identify how the repair is accomplished.

Abstract: Structures for fuses to control repair of multiple memories embedded on an integrated circuit are provided along with methods of use. A set of fuses is shared to control repair of a plurality of memories. Some of the fuses are associated with a memory to be repaired. Others of the fuses identify how the repair is accomplished.

Abstract: A method and a circuit are given, to implement and realize power saving Sense Electronics Endowed (SEE) memory using modified memory read cycles, named as Smart Memory Readout (SMR). In an SMR-mode read cycle, the memory is only active a small fraction of a clock cycle thus saving power. In this small fraction where the memory is enabled by SMR-mode read, the memory content is read to a shadow register and held until read by the microcontroller. Said circuit and method are designed in order to be implemented with a very economic number of components, capable to be realized with modern integrated circuit technologies.

Abstract: A central processor unit (CPU) accesses memory to read and write data and to read and execute program instructions. A problem arises when accessing slower Flash or electrically programmable read only memory (EPROM) with a faster CPU. A method and system has been devised which uses interleaving techniques and memory sub-sections. A memory interlace controller interfaces a faster CPU to several sub-sections of slower memory. The memory interlace controller interlaces the access of the slower memory and thus optimizing the CPU system speed.

Abstract: A circuit and a method are given, to realize a dynamically adapting response speed behavior of memory sense electronics for Sense Electronics Endowed (SEE) memory devices. Fast memories use sense amplifiers in the read path in order to react fast with the data being delivered from a given address position. In order to achieve short response times, these sense amplifiers are normally responding very fast with accordingly high power consumption. Dynamically reducing the response speed after a certain “on” time of operation will save power for fast memories used in conditions where the utmost speed is not needed. Said circuit and method are designed in order to be implemented with a very economic number of components, capable to be realized with modern integrated circuit technologies.

Abstract: A circuit and a method are given, to realize a dynamically adapting response speed behavior of memory sense electronics for Sense Electronics Endowed (SEE) memory devices. Fast memories use sense amplifiers in the read path in order to react fast with the data being delivered from a given address position. In order to achieve short response times, these sense amplifiers are normally responding very fast with accordingly high power consumption. Dynamically reducing the response speed after a certain “on” time of operation will save power for fast memories used in conditions where the utmost speed is not needed. Said circuit and method are designed in order to be implemented with a very economic number of components, capable to be realized with modern integrated circuit technologies.

Abstract: A circuit and a method are given, to realize a dynamical biasing of memory sense amplifiers for Sense Electronics Endowed (SEE) memory devices. Fast memories uses sense amplifiers in the read path in order to react fast with the data being delivered from a given address position. In order to achieve short response times, these sense amplifiers are normally supplied with a high bias current. Dynamically reducing the bias current after a certain “on” time of operation will save power for fast memories used in conditions where the utmost speed is not needed. Said circuit and method are designed in order to be implemented with a very economic number of components, capable to be realized with modern integrated circuit technologies.

Abstract: The power consumption when the memory is accessed is often a concern for low power microcontroller systems. Specifically it is desirable to minimize the power consumption during the often very long periods of processor idling time. The invention presented implements a power saving technique by replacing the program memory, containing the idle-program-routine with a simple hard wired address-decoder and coded-data-driver to produce the very few program instructions to run the processor in a permanent loop. The minimum implementation just produces the few bytes for a single instruction to jump back to its own address. As there are very few circuits involved, its memory power consumptions is nearly zero.

Abstract: A circuit and a method are given, to realize a dynamical biasing of memory sense amplifiers for Sense Electronics Endowed (SEE) memory devices. Fast memories uses sense amplifiers in the read path in order to react fast with the data being delivered from a given address position. In order to achieve short response times, these sense amplifiers are normally supplied with a high bias current. Dynamically reducing the bias current after a certain “on” time of operation will save power for fast memories used in conditions where the utmost speed is not needed. Said circuit and method are designed in order to be implemented with a very economic number of components, capable to be realized with modern integrated circuit technologies.

Abstract: A method and a circuit are given, to implement and realize power saving Sense Electronics Endowed (SEE) memory using modified memory read cycles, named as Smart Memory Readout (SMR). In an SMR-mode read cycle, the memory is only active a small fraction of a clock cycle thus saving power. In this small fraction where the memory is enabled by SMR-mode read, the memory content is read to a shadow register and held until read by the microcontroller. Said circuit and method are designed in order to be implemented with a very economic number of components, capable to be realized with modern integrated circuit technologies.

Abstract: A central processor unit (CPU) accesses memory to read and write data and to read and execute program instructions. A problem arises when accessing slower Flash or electrically programmable read only memory (EPROM) with a faster CPU. A method and system has been devised which uses interleaving techniques and memory sub-sections. A memory interlace controller interfaces a faster CPU to several sub-sections of slower memory. The memory interlace controller interlaces the access of the slower memory and thus optimizing the CPU system speed.

Abstract: A new method to detect and to correct a weakly programmed cell in a nonvolatile memory device is achieved. The method comprises providing a plurality of nonvolatile memory cells. A means to read a selected cell compares the performance of the selected cell with the performance of a reference cell. A read state of the selected cell is high if the selected cell exceeds the reference cell. The read state of the selected cell is low if the selected cell exceeds the reference cell. A first read state is obtained by reading the selected cell with the reference cell biased to a first value. A second read state is obtained by reading the selected cell with the reference cell biased to a second value that is greater than the first value. The selected cell is flagged as weakly programmed, high if the first and second read states do not match. A third read state is obtained by reading the selected cell with the reference cell biased to a third value that is less than the first value.

Abstract: A new method to detect and to correct a weakly programmed cell in a nonvolatile memory device is achieved. The method comprises providing a plurality of nonvolatile memory cells. A means to read a selected cell compares the performance of the selected cell with the performance of a reference cell. A read state of the selected cell is high if the selected cell exceeds the reference cell. The read state of the selected cell is low if the selected cell exceeds the reference cell. A first read state is obtained by reading the selected cell with the reference cell biased to a first value. A second read state is obtained by reading the selected cell with the reference cell biased to a second value that is greater than the first value. The selected cell is flagged as weakly programmed, high if the first and second read states do not match. A third read state is obtained by reading the selected cell with the reference cell biased to a third value that is less than the first value.