Patents by Inventor Thomas Aichinger

Thomas Aichinger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11940489
    Abstract: A semiconductor device includes: a semiconductor body; an electrical device formed in an active region of the semiconductor body, the active region including an interface between the semiconductor body and an insulating material; and a sensor having a bandwidth tuned to at least part of an energy spectrum of light emitted by carrier recombination at the interface when the electrical device is driven between accumulation and inversion, wherein an intensity of the emitted light is proportional to a density of charge trapping states at the interface, wherein the sensor is configured to output a signal that is proportional to the intensity of the sensed light. Corresponding methods of monitoring and characterizing the semiconductor device and a test apparatus are also described.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: March 26, 2024
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Maximilian Wolfgang Feil, Andre Kabakow, Hans Reisinger
  • Patent number: 11881512
    Abstract: A method includes providing a silicon carbide substrate, wherein a gate trench extends from a main surface of the silicon carbide substrate into the silicon carbide substrate and wherein a gate dielectric is formed on at least one sidewall of the gate trench, and forming a gate electrode in the gate trench, the gate electrode including a metal structure and a semiconductor layer between the metal structure and the gate dielectric.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: January 23, 2024
    Assignee: Infineon Technologies AG
    Inventors: Ralf Siemieniec, Thomas Aichinger, Romain Esteve, Ravi Keshav Joshi, Shiqin Niu
  • Publication number: 20230411460
    Abstract: A method of producing a semiconductor device includes forming a plurality of transistor cells in a SiC substrate and electrically connected in parallel to form a transistor having a specified operating temperature range. Forming each transistor cell includes forming a gate structure having a gate electrode, and a gate dielectric stack separating the gate electrode from the SiC substrate and including a ferroelectric insulator. The method further includes doping the ferroelectric insulator with a doping material such that the Curie temperature of the ferroelectric insulator is in a range above the specified operating temperature range of the transistor.
    Type: Application
    Filed: September 5, 2023
    Publication date: December 21, 2023
    Inventors: Saurabh Roy, Thomas Aichinger, Hans-Joachim Schulze
  • Publication number: 20230352520
    Abstract: A wide band gap semiconductor device includes a semiconductor body having first and second opposing surfaces along a vertical direction. Trench gate structures extend into the semiconductor body from the first surface and include a gate electrode structure and a gate dielectric structure arranged between the gate electrode structure and the semiconductor body. The gate dielectric structure includes a high-k dielectric layer. A first sidewall of a trench gate structure adjoins a first mesa region. A second sidewall of the trench gate structure adjoins a second mesa region. The first mesa region includes a body region of a first conductivity type adjoining the first sidewall. The second mesa region includes a shielding region of the first conductivity type. A bottom side of the shielding region has a larger first vertical distance to the first surface than a bottom side of the body region in the first mesa region.
    Type: Application
    Filed: April 21, 2023
    Publication date: November 2, 2023
    Inventor: Thomas Aichinger
  • Patent number: 11791383
    Abstract: A semiconductor device includes a SiC substrate and a plurality of transistor cells formed in the SiC substrate and electrically connected in parallel to form a transistor. Each transistor cell includes a gate structure including a gate electrode and a gate dielectric stack separating the gate electrode from the SiC substrate. The gate dielectric stack includes a ferroelectric insulator. The transistor has a specified operating temperature range, and the ferroelectric insulator is doped with a doping material such that the Curie temperature of the ferroelectric insulator is in a range above the specified operating temperature range of the transistor. A corresponding method of producing the semiconductor device is also described.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: October 17, 2023
    Assignee: Infineon Technologies AG
    Inventors: Saurabh Roy, Thomas Aichinger, Hans-Joachim Schulze
  • Publication number: 20230178615
    Abstract: A power transistor device includes a semiconductor substrate, a gate trench extending into the semiconductor substrate, a transistor gate provided in the gate trench, and an insulating structure formed between the transistor gate and a side wall of the gate trench. The insulating structure is configured to electrically insulate the transistor gate from a channel region which extends along the side wall of the gate trench. The insulating structure includes a layer of piezoelectric material.
    Type: Application
    Filed: December 1, 2022
    Publication date: June 8, 2023
    Inventors: Saurabh Roy, Hans-Joachim Schulze, Oliver Blank, Josef Anton Moser, Thomas Aichinger
  • Publication number: 20230121426
    Abstract: A semiconductor device includes: a semiconductor body; an electrical device formed in an active region of the semiconductor body, the active region including an interface between the semiconductor body and an insulating material; and a sensor having a bandwidth tuned to at least part of an energy spectrum of light emitted by carrier recombination at the interface when the electrical device is driven between accumulation and inversion, wherein an intensity of the emitted light is proportional to a density of charge trapping states at the interface, wherein the sensor is configured to output a signal that is proportional to the intensity of the sensed light. Corresponding methods of monitoring and characterizing the semiconductor device and a test apparatus are also described.
    Type: Application
    Filed: October 15, 2021
    Publication date: April 20, 2023
    Inventors: Thomas Aichinger, Maximilian Wolfgang Feil, Andre Kabakow, Hans Reisinger
  • Patent number: 11626477
    Abstract: A semiconductor component includes: gate structures extending from a first surface into an SiC semiconductor body; a drift zone of a first conductivity type formed in the SiC semiconductor body; first mesas and second mesas arranged between the gate structures in the SiC semiconductor body; body areas of a second conductivity type arranged in the first mesas and the second mesas, the body areas each adjoining a first side wall of one of the gate structures; first shielding areas of the second conductivity type adjoining a second side wall of one of the gate structures; second shielding areas of the second conductivity type adjoining the body areas in the second mesas; and diode areas of the conductivity type of the drift zone, the diode areas forming Schottky contacts with a load electrode between the first shielding areas and the second shielding areas.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: April 11, 2023
    Assignee: Infineon Technologies AG
    Inventors: Ralf Siemieniec, Thomas Aichinger, Thomas Basler, Wolfgang Bergner, Rudolf Elpelt, Romain Esteve, Michael Hell, Daniel Kueck, Caspar Leendertz, Dethard Peters, Hans-Joachim Schulze
  • Publication number: 20230035144
    Abstract: A semiconductor device includes a SiC substrate and a plurality of transistor cells formed in the SiC substrate and electrically connected in parallel to form a transistor. Each transistor cell includes a gate structure including a gate electrode and a gate dielectric stack separating the gate electrode from the SiC substrate. The gate dielectric stack includes a ferroelectric insulator. The transistor has a specified operating temperature range, and the ferroelectric insulator is doped with a doping material such that the Curie temperature of the ferroelectric insulator is in a range above the specified operating temperature range of the transistor. A corresponding method of producing the semiconductor device is also described.
    Type: Application
    Filed: July 28, 2021
    Publication date: February 2, 2023
    Inventors: Saurabh Roy, Thomas Aichinger, Hans-Joachim Schulze
  • Patent number: 11462611
    Abstract: A semiconductor device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. A trench interval which defines a space between adjacent gate trenches extends in a second direction perpendicular to the first direction. Source regions of a first conductivity type formed in the SiC substrate occupy a first part of the space between adjacent gate trenches. Body regions of a second conductivity type opposite the first conductivity type formed in the SiC substrate and below the source regions occupy a second part of the space between adjacent gate trenches. Body contact regions of the second conductivity type formed in the SiC substrate occupy a third part of the space between adjacent gate trenches. Shielding regions of the second conductivity type formed deeper in the SiC substrate than the body regions adjoin a bottom of at least some of the gate trenches.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: October 4, 2022
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Wolfgang Bergner, Paul Ellinghaus, Rudolf Elpelt, Romain Esteve, Florian Grasse, Caspar Leendertz, Shiqin Niu, Dethard Peters, Ralf Siemieniec, Bernd Zippelius
  • Publication number: 20220262906
    Abstract: A silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) and a method for forming a SiC MOSFET are disclosed. In an example, the method includes forming a gate dielectric that adjoins a body region arranged in a semiconductor body, and forming a gate electrode on the gate dielectric. Forming the gate electrode includes forming a first electrode layer, implanting work function adjusting atoms into the first electrode layer, and forming a second electrode layer on the first electrode layer.
    Type: Application
    Filed: February 15, 2022
    Publication date: August 18, 2022
    Inventors: Ralf SIEMIENIEC, Thomas AICHINGER, Ravi Keshav JOSHI, Werner SCHUSTEREDER
  • Patent number: 11417747
    Abstract: In an example, a transistor device is provided. The transistor device includes a plurality of transistor cells each including a gate electrode and each at least partially integrated in a semiconductor body that includes a wide bandgap semiconductor material. The transistor device includes a gate pad arranged on top of the semiconductor body, and a plurality of gate runners each arranged on top of the semiconductor body and each connected to gate electrodes of at least some of the plurality of transistor cells. Each gate runner of the plurality of gate runners has a longitudinal direction, and at least one of the gate runners includes at least a section in which a resistivity per area increases in the longitudinal direction as a distance to the gate pad along the gate runner increases.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: August 16, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Aichinger, Wolfgang Bergner, Ralf Siemieniec, Frank Wolter
  • Publication number: 20220246745
    Abstract: A silicon carbide device includes a semiconductor substrate comprising a body region and transistor cell that comprises a source region, and a titanium carbide field electrode of the transistor cell, wherein the titanium carbide field electrode is connected to a reference voltage metallization structure or connectable to the reference voltage metallization structure by a switching device, wherein the reference voltage metallization is connected to a fixed voltage that is independent from a gate voltage of the transistor cell.
    Type: Application
    Filed: April 22, 2022
    Publication date: August 4, 2022
    Inventors: Ralf Siemieniec, Thomas Aichinger, Iris Moder, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze, Carsten von Koblinski
  • Patent number: 11342433
    Abstract: A silicon carbide device includes a silicon carbide substrate having a body region and a source region of a transistor cell. Further, the silicon carbide device includes a titanium carbide gate electrode of the transistor cell.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: May 24, 2022
    Assignee: Infineon Technologies AG
    Inventors: Ralf Siemieniec, Thomas Aichinger, Iris Moder, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze, Carsten von Koblinski
  • Publication number: 20220157607
    Abstract: A method for forming a wide band gap semiconductor device is provided. The method includes forming a gate insulation layer on a wide band gap semiconductor substrate and annealing the gate insulation layer using at least a first reactive gas species and a second reactive gas species, wherein the first reactive gas species differs from the second reactive gas species. The method can include forming a gate electrode on the gate insulation layer after annealing the gate insulation layer.
    Type: Application
    Filed: February 8, 2022
    Publication date: May 19, 2022
    Inventors: Thomas Aichinger, Gerald Rescher, Michael Stadtmueller
  • Patent number: 11295951
    Abstract: A method for forming a wide band gap semiconductor device is provided. The method includes forming a gate insulation layer on a wide band gap semiconductor substrate and annealing the gate insulation layer using at least a first reactive gas species and a second reactive gas species, wherein the first reactive gas species differs from the second reactive gas species. The method can include forming a gate electrode on the gate insulation layer after annealing the gate insulation layer.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: April 5, 2022
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Gerald Rescher, Michael Stadtmueller
  • Publication number: 20220059659
    Abstract: A method includes providing a silicon carbide substrate, wherein a gate trench extends from a main surface of the silicon carbide substrate into the silicon carbide substrate and wherein a gate dielectric is formed on at least one sidewall of the gate trench, and forming a gate electrode in the gate trench, the gate electrode including a metal structure and a semiconductor layer between the metal structure and the gate dielectric.
    Type: Application
    Filed: November 4, 2021
    Publication date: February 24, 2022
    Inventors: Ralf Siemieniec, Thomas Aichinger, Romain Esteve, Ravi Keshav Joshi, Shiqin Niu
  • Patent number: 11251269
    Abstract: An embodiment of a semiconductor device includes a trench gate structure extending from a first surface into a silicon carbide semiconductor body along a vertical direction. A body region of a first conductivity type adjoins a sidewall of the trench gate structure and includes a first body sub-region adjoining the sidewall and a second body sub-region adjoining the sidewall. At least one profile of dopants of the first conductivity type along the vertical direction includes a first doping peak in the first body sub-region and a second doping peak in the second body sub-region. A doping concentration of the first doping peak is larger than a doping concentration of the second doping peak.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: February 15, 2022
    Assignee: Infineon Technologies AG
    Inventors: Reinhard Ploss, Thomas Aichinger, Roland Rupp, Hans-Joachim Schulze
  • Patent number: 11195921
    Abstract: A semiconductor device includes a gate electrode and a gate dielectric. The gate electrode extends from a first surface of a silicon carbide body into the silicon carbide body. The gate dielectric is between the gate electrode and the silicon carbide body. The gate electrode includes a metal structure and a semiconductor layer between the metal structure and the gate dielectric.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: December 7, 2021
    Assignee: Infineon Technologies AG
    Inventors: Ralf Siemieniec, Thomas Aichinger, Romain Esteve, Ravi Keshav Joshi, Shiqin Niu
  • Publication number: 20210343835
    Abstract: A semiconductor component includes: gate structures extending from a first surface into an SiC semiconductor body; a drift zone of a first conductivity type formed in the SiC semiconductor body; first mesas and second mesas arranged between the gate structures in the SiC semiconductor body; body areas of a second conductivity type arranged in the first mesas and the second mesas, the body areas each adjoining a first side wall of one of the gate structures; first shielding areas of the second conductivity type adjoining a second side wall of one of the gate structures; second shielding areas of the second conductivity type adjoining the body areas in the second mesas; and diode areas of the conductivity type of the drift zone, the diode areas forming Schottky contacts with a load electrode between the first shielding areas and the second shielding areas.
    Type: Application
    Filed: July 14, 2021
    Publication date: November 4, 2021
    Inventors: Ralf Siemieniec, Thomas Aichinger, Thomas Basler, Wolfgang Bergner, Rudolf Elpelt, Romain Esteve, Michael Hell, Daniel Kueck, Caspar Leendertz, Dethard Peters, Hans-Joachim Schulze