Abstract: A clearance control ring having at least two segments is disclosed. Each of the segments interlock with adjacent segments to form a full hoop clearance control ring. Separate carriers and seals or one-piece carriers and seals may be mounted on the clearance control ring. The segmented structure of the clearance control ring allows for simpler assembly with segmented cases for gas turbine engines than prior art one-piece clearance control rings. The segmented structure also may be used with one-piece pre-assembled and multi-stage rotors.

Abstract: A radial position control assembly for a gas turbine engine stage includes a case structure. A supported structure is operatively supported by the case structure. A support ring operatively supports the supported structure. The supported structure and the support ring have different coefficients of thermal expansion. A sealing structure is adjacent to the supported structure. The support ring maintains the supported structure relative to the sealing structure at a clearance during thermal transients based upon a circumferential gap between adjacent supported structure and based upon a radial gap between the support ring and the supported structure. A pin supports the supported structure relative to the case structure and is configured to isolate the support ring from loads on the supported structure.

Abstract: A control ring extends circumferentially about a central axis. A plurality of circumferentially spaced carrier portions have a cavity receiving the control ring. There are circumferential gaps between the carrier portions. A blade outer air seal is mounted on the carrier portions radially inwardly of the control ring. The control ring maintains the carrier portions at a radially outwardly expanded position when heated by an electric heater.

Abstract: A blade outer air seal system for a gas turbine engine includes a plurality of ring carriers made of a first material having a first coefficient of thermal expansion. A plurality of seal segments are carried, respectively, on the plurality of ring carriers. A ring member is carried in the plurality of ring carriers. The ring member is made of a second material that is different from the first material in composition. The second material has a second coefficient of thermal expansion such that the first coefficient of thermal expansion is 75-175% of the second coefficient of thermal expansion.

Abstract: A radial position control assembly for a gas turbine engine stage includes a case structure. A supported structure is operatively supported by the case structure. A support ring operatively supports the supported structure. The supported structure and the support ring have different coefficients of thermal expansion. A sealing structure is adjacent to the supported structure. The support ring maintains the supported structure relative to the sealing structure at a clearance during thermal transients based upon a circumferential gap between adjacent supported structure and based upon a radial gap between the support ring and the supported structure. A pin supports the supported structure relative to the case structure and is configured to isolate the support ring from loads on the supported structure.

Abstract: A control ring extends circumferentially about a central axis. A plurality of circumferentially spaced carrier portions have a cavity receiving the control ring. There are circumferential gaps between the carrier portions. A blade outer air seal is mounted on the carrier portions radially inwardly of the control ring. The control ring maintains the carrier portions at a radially outwardly expanded position when heated by an electric heater.

Abstract: A clearance control ring having at least two segments is disclosed. Each of the segments interlock with adjacent segments to form a full hoop clearance control ring. Separate carriers and seals or one-piece carriers and seals may be mounted on the clearance control ring. The segmented structure of the clearance control ring allows for simpler assembly with segmented cases for gas turbine engines than prior art one-piece clearance control rings. The segmented structure also may be used with one-piece pre-assembled and multi-stage rotors.

Abstract: A blade outer air seal system for a gas turbine engine includes a plurality of ring carriers made of a first material having a first coefficient of thermal expansion. A plurality of seal segments are carried, respectively, on the plurality of ring carriers. A ring member is carried in the plurality of ring carriers. The ring member is made of a second material that is different from the first material in composition. The second material has a second coefficient of thermal expansion such that the first coefficient of thermal expansion is 75-175% of the second coefficient of thermal expansion.

Abstract: A triggering circuit asserts a trigger signal in response to edges of a digital signal conveying a repetitive pattern of edges. The triggering circuit generates first data having a value identifying a position within the pattern of a last occurring edge of the digital signal and generates second data having a value identifying a position of a particular edge within the pattern that is to initiate a next assertion of the trigger signal. The triggering circuit asserts the trigger signal when the first and second data values match and de-asserts the trigger signal when the first and second data do not match. In a repetitive mode of operation, the triggering circuit keeps the second data value constant so that it always asserts the trigger signal in response to the same edge of the pattern.

Abstract: An electronic device under test (DUT) responds to a digital input signal by generating a digital DUT output signal conveying a repetitive digital signal pattern. An apparatus for measuring various characteristics of the DUT output signal includes a trigger generator for generating a series of trigger signal edges in response to selected DUT output signal edges occurring during separate repetitions of the digital signal pattern. The trigger generator can be configured to generate each trigger signal edge in response to the same or a different edge of the digital signal pattern. The apparatus determines when a DUT output signal edge occurs by determining when the DUT output signal rises above or falls below adjustable reference voltages. The apparatus alternatively responds to each trigger signal edge by measuring a period between two different edges of the digital signal pattern and or by repetitively sampling the DUT output signal to determine its state.

Abstract: An integrated circuit tester channel includes an integrated circuit (IC) for adding a programmably controlled amount of jitter to a digital test signal to produce a DUT input signal having a precisely controlled jitter pattern. The IC also measures periods between selected edges of the same or different ones of the DUT output signal, the DUT input signal, and a reference clock signal. Additionally, when the DUT input and output signals convey repetitive patterns, the IC can measure the voltage of the DUT input out output signal as selected points within the pattern by comparing it to an adjustable reference voltage. Processing circuits external to the IC program the IC to provide a specified amount of jitter to the test signal, control the measurements carried out by the measurement circuit, and process measurement data to determine the amount of jitter and other characteristics of the DUT output signal, and to calibrate the jitter in the DUT input signal.

Abstract: A method for evaluating an electrical signal is disclosed. This method is especially useful for evaluating analog signals within an integrated circuit or other inaccessible location. A reference histogram is derived from either a simulation of a desired waveform or from sampling a desired waveform signal. This reference histogram is subtracted from a test results histogram to produce a variance histogram. The variance histogram can be further evaluated to determine characteristics of the electrical signal under test and/or to produce a figure of merit for the circuitry producing the signal under evaluation. Before the difference between the test results histogram and the reference histogram is taken, normalization, offset calculation, gain adjustment, and noise floor adjustment may be performed on the test results histogram, and these values may be exported to further aid in characterization of the signal under evaluation.

Abstract: An embedded electronic system includes a clock controller embedded in the same matrix material as a subsystem under test and the measurement devices needed to test it. This embedded clock controller controls the distribution and gating of a system clock that runs continuously, but is only supplied to the subsystem under test during normal operation or during pre-programmed intervals of testing operations. A test data bus supplies test data and a path for the return of test results. The test data supplied to the clock controller includes information to control time relationships between its trigger and gated clock outputs. Different versions of the clock controller are described, one for use with a serial test data bus and another for use with a parallel test data bus. The clock controller can also be configured to produce trigger signals with timing appropriate to operating either edge-sensitive or level-sensitive measurement devices.

Abstract: An adjustable precision delay circuit includes a series of inverter gates and a multiplexer for selecting any of their outputs or the input to the series. The polarity of the signal input to this circuit is controlled so that any selected output always has the same predetermined polarity, thereby eliminating timing errors arising from factors that vary with the polarity of the output.

Abstract: A variable reference voltage generator provides variable voltage rails for a delay element in order to control the amount of delay of an electrical signal through the delay element. A control signal, such as an error signal from a phase locked loop, is input to a pair of operational amplifiers, one configured as a unity gain buffer and the other configured as a positive gain feedback amplifier. The one amplifier is coupled to one input of a modified Magee inverter circuit and the other amplifier is coupled to the other input of the modified Magee inverter circuit. The variable voltage rails are taken from the output buffers of the modified Magee inverter circuit. To provide a range of voltages for the variable voltage rails that approaches the power supply voltages, the two outer transistors of the modified Magee inverter circuit are converted to voltage sources so that the control signal is added to the positive power supply voltage and subtracted from the negative power supply voltage.

Abstract: A timing analyzer for embedded testing of printed circuit boards, integrated circuits or multi-chip modules is in the form of an integrated circuit that may be included as part of the printed circuit board, integrated circuit or multi-chip module being tested. Each channel of a data path to be tested has a timing analyzer circuit that may be coupled into the path when enabled for testing. The timing analyzer circuit has instruction memories that are loaded with time event commands via a suitable program bus, such as a boundary scan interface. Each event command has a clock portion, an interpolation portion and a drive output portion. A counter counts down the clock portion using a system clock from the board/circuit/module to produce a terminate pulse. The terminate pulse is delayed by an increment less than one period of the system clock by a delay interpolator, the amount of delay being determined by the interpolation portion, to generate a trigger signal.

Abstract: A low distortion optic fiber network having a feedback system which injects pilot tones into a base band input signal directly modulating an LED, optically detects the output resulting from the pilot tones, digitally samples the detected signal, and generates correction coefficients. The correction coefficients and the base band input signal are input to a correction circuit that pre-distorts the input signal in a non-linear manner and uses the distorted signal to modulate the LED. Pre-distorting the LED input signal compensates for the non-linearities of diode transfer characteristics and intermodulation between signals in the network thereby reducing harmonic and intermodulation distortion.

Abstract: An associative memory having a large storage capacity which also has the capability of being used as a conventional memory, i.e. accessed by physical location. A memory array (11) is accessed in conventional fashion by an address decoder (15). A mask/data drive circuit (13) controls the loading/reading of the memory array (11) when the device is in a conventional mode, and operates on the same pins to provide mask and search data when the drive is in the associative mode. In the associative mode, a plurality of match detect (17) circuits, one for each word location in memory (11), receive the output signals from the memory array (11). The match detect circuits (17) prioritize the output match signals from memory (11) and provide an output indicating the first or lowest word in memory (11) having a match. An address encoder (19) is responsive to the prioritized match output (if any) from the match detect circuits (17) to determine the physical location in memory (11) containing the matched word.

Abstract: A circuit (11) for use in an associative memory device, one such circuit being associated with each word location in memory, for indicating a match when the word associated with a given circuit (11) is a match for a current portion of a search pattern and the previous word is a match for a previous portion of the search pattern. In operation of the circuit (11), a latch (23) is initialized to a match condition, and provides a match output, which is also applied to the next successive circuit, for the next successive word in memory. The latch (23) is controlled by an AND gate (21), to which is applied the output signal from the circuit for the previous word in memory and a signal indicating a match or non-match for the word in memory associated with circuit (11) containing AND gate (21).