Abstract: A power supply generates a power supply signal to provide electric power over a USB type-C bus. The power supply includes temperature sensing circuitry which senses indications of temperature of the power supply. Control circuitry coupled to the power supply circuitry and the temperature sensing circuitry compares indications of temperature sensed by the temperature sensing circuitry to three thresholds. The control circuitry determines a limit on available electric power provided by the power supply circuitry over the USB type-C bus based on the comparing. The limit on available electric power is set to one of three or more power levels based on the comparing.

Abstract: A power consumption measurement method for operating an electronic component during an interval of time includes: logging power states that the component adopts during the interval, interrogating the log to determine the amount of time that the component spent in each power state during interval, and multiplying the rated power consumption for each state by the amount of time spent in each respective state. The power consumptions for each of the states are summed to determine a total power consumption of the component during the interval. Logging the power states may be achieved by counting command line instructions of different types, thus identify the beginning and end of each power state, during the interval. The method may be used to measure and/or benchmark the actual power consumption of a DDR RAM module. An apparatus for carrying out the method is also disclosed.

Abstract: There is disclosed a solution for obtaining Memory Access Performance metrics in an electronic system comprising a Data Processing Unit, DPU and a synchronous memory device external to the DPU and coupled to the DPU through a memory bus. There is used mixed software and hardware dedicated resources, wherein at least a hardware part of the dedicated resources is comprised in the memory device.

Abstract: The sequential access memory array is able to store p words each of n bits. Such p test words each made up of n test bits are written in the memory array, the p test words are extracted sequentially and, for each current word extracted, the n test bits that compose it are compared sequentially with n respective expected data bits before extracting the next test word.

Abstract: A method of transferring guard values and a computer system, such as a processor for digital signal processing, including a parallel set of execution units that utilizes the method. A master set of guard indicators is held in association with one of the execution units. If other execution units require the guard values for particular guard indicators, a sendguard instruction is issued to the execution unit holding the master guard values. The sendguard instructions are held in a separate queue from the main instructions intended for that execution unit. Circuitry is provided in the execution unit to avoid stalling in the dispatch of sendguard instructions even in the context of earlier guard modifying instructions.

Abstract: A device generates an address branch trace for a microcontroller unit, a microprocessor or a data processing unit having a set of instructions including at least one predicated instruction and at least one instruction of the expanded type. The device includes: a first block to receive a first signal representative of an actually executed instruction; a second block to receive a second signal representative of an expanded instruction; a third block to receive a third signal representative of a discontinuity branch between a source address and a destination address of a program executed by the microcontroller, microprocessor or data processing unit; at least one register to store consecutive addresses pointed to by a program counter; a fourth block to process the first, second and third signals in order to determine a pair having a source address and a destination address for an address branch, when appropriate; and a storage unit to store said address pair.

Abstract: A device for generating an address branch trace for a microcontroller unit, a microprocessor or a data processing unit having a set of instructions including at least one predicated instruction and at least one instruction of the expanded type, said device including: means for receiving a first signal representative of an actually executed instruction; means for receiving a second signal representative of an expanded instruction; means for receiving a third signal representative of a discontinuity branch between a source address and a destination address of a program executed by said microcontroller, microprocessor or data processing unit; means for storing consecutive addresses pointed by a program counter; means for processing said first, second and third signals in order to determine a pair comprised of a source address and a destination address for an address branch, when appropriate; and means for storing said address pair.

Abstract: A method of transferring guard values and a computer system, such as a processor for digital signal processing, including a parallel set of execution units that utilizes the method. A master set of guard indicators is held in association with one of the execution units. If other execution units require the guard values for particular guard indicators, a sendguard instruction is issued to the execution unit holding the master guard values. The sendguard instructions are held in a separate queue from the main instructions intended for that execution unit. Circuitry is provided in the execution unit to avoid stalling in the dispatch of sendguard instructions even in the context of earlier guard modifying instructions.

Abstract: A method of transferring guard values and a computer system, such as a processor for digital signal processing, including a parallel set of execution units that utilizes the method. A master set of guard indicators is held in association with one of the execution units. If other execution units require the guard values for particular guard indicators, a sendguard instruction is issued to the execution unit holding the master guard values. The sendguard instructions are held in a separate queue from the main instructions intended for that execution unit. Circuitry is provided in the execution unit to avoid stalling in the dispatch of sendguard instructions even in the context of earlier guard modifying instructions.

Abstract: A multiplexed flip-flop electronic device includes a decoder logic circuit for providing a first switching signal, and a control circuit for receiving a clock signal and for providing a gated clock signal forming a second switching signal. The electronic device further includes a multiplexing circuit having N inputs and an output, and a flip flop circuit. The flip-flop circuit includes a first switching stage connected between the N inputs and the output of the multiplexing circuit, and includes N switches being individually controlled by the first switching signal. A first buffer stage is connected to the output of the multiplexing circuit, and a second switching stage is connected to an output of the first buffer stage. The second switching stage is controlled by the second switching signal. A second buffer stage is connected to an output of the second switching stage.

Abstract: A multiplexed flip-flop electronic device includes a decoder logic circuit for providing a first switching signal, and a control circuit for receiving a clock signal and for providing a gated clock signal forming a second switching signal. The electronic device further includes a multiplexing circuit having N inputs and an output, and a flip flop circuit. The flip-flop circuit includes a first switching stage connected between the N inputs and the output of the multiplexing circuit, and includes N switches being individually controlled by the first switching signal. A first buffer stage is connected to the output of the multiplexing circuit, and a second switching stage is connected to an output of the first buffer stage. The second switching stage is controlled by the second switching signal. A second buffer stage is connected to an output of the second switching stage.

Abstract: The sequential access memory array is able to store p words each of n bits. Such p test words each made up of n test bits are written in the memory array, the p test words are extracted sequentially and, for each current word extracted, the n test bits that compose it are compared sequentially with n respective expected data bits before extracting the next test word.

Abstract: A circuit for controlling the storage of data in a memory element including a bistable device having a first input for receiving an address input and a second input for receiving a clock signal and circuitry for receiving the output of the bistable device and the clock signal and providing a write enable signal for the memory, the circuitry being arranged so that the write enable signal is enabled in response to a first transition in the clock signal from a first state to a second state and disabled in response to the clock signal making the next transition back to the first state, the first and next transitions being in the same clock cycle.