Patents by Inventor Thomas Andrew Sartorius

Thomas Andrew Sartorius has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10114756
    Abstract: A method includes reading, by a processor, one or more configuration values from a storage device or a memory management unit. The method also includes loading the one or more configuration values into one or more registers of the processor. The one or more registers are useable by the processor to perform address translation.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 30, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Christopher Edward Koob, Erich James Plondke, Piyush Patel, Thomas Andrew Sartorius, Lucian Codrescu
  • Publication number: 20180173631
    Abstract: Systems and methods are directed to prefetch mechanisms involving non-equal magnitude stride values. A non-equal magnitude functional relationship between successive stride values, may be detected, wherein the stride values are based on distances between target addresses of successive load instructions. At least a next stride value for prefetching data, may be determined, wherein the next stride value is based on the non-equal magnitude functional relationship and a previous stride value. Data prefetch may be from at least one prefetch address calculated based on the next stride value and a previous target address. The non-equal magnitude functional relationship may include a logarithmic relationship corresponding to a binary search algorithm.
    Type: Application
    Filed: May 14, 2017
    Publication date: June 21, 2018
    Inventors: Thomas Andrew SARTORIUS, James Norris DIEFFENDERFER, Thomas Philip SPEIER, Michael Scott MCILVAINE, Michael William MORROW
  • Publication number: 20170255569
    Abstract: Systems and methods for managing access to a cache relate to determining one or more execute permissions associated with a write-address of a write-request to the cache. The cache may be a unified cache for storing data as well as instructions. If there is a write-miss in the cache for the write-request, a cache controller may determine whether to implement a write-allocate policy or a write-no-allocate policy for servicing the write-miss, based on the one or more execute permissions. The one or more execute permissions can relate to a privilege level associated with the write-address. Execute permissions of a producing agent which generated the write-request and an execute permission of a consuming agent which can execute from the write-address may be based on the privilege levels of the producing agent and the consuming agent, respectively.
    Type: Application
    Filed: March 1, 2016
    Publication date: September 7, 2017
    Inventors: Thomas Andrew SARTORIUS, James Norris DIEFFENDERFER, Michael William MORROW, Jeffrey Todd BRIDGES, Michael Scott MCILVAINE, Rodney Wayne SMITH, Kenneth Alan DOCKSER, Thomas Philip SPEIER
  • Patent number: 9710269
    Abstract: Delays due to waiting for operands that will not be used by a select operand instruction, are alleviated based on an early recognition that such operand data is not required in order to complete the processing of the select operand instruction. At appropriate points prior to execution, determinations are made regarding a selection criterion or criteria specified by the select operand instruction, conditions that affect the selection criteria, and the availability of operands. A hold circuit uses the determinations to control the activation and release of a hold signal that controls processor pipeline stalls. A stall required to wait for operand data is skipped or a stall is terminated early, if the selected operand is available even though the other operand, that will not be used, is not available. A stall due to waiting for operands is maintained until the selection criteria is met and the selected operand is fetched and made available.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: July 18, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: James Norris Dieffenderfer, Jeffrey Todd Bridges, Michael Scott McIlvaine, Thomas Andrew Sartorius
  • Publication number: 20170091117
    Abstract: A cache fill line is received, including an index, a thread identifier, and cache fill line data. The cache is probed, using the index and a different thread identifier, for a potential duplicate cache line. The potential duplicate cache line includes cache line data and the different thread identifier. Upon the cache fill line data matching the cache line data, duplication is identified. The potential duplicate cache line is set as a shared resident cache line, and the thread share permission tag is set to a permission state.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Inventors: Harold Wade CAIN, III, Derek Robert HOWER, Raguram DAMODARAN, Thomas Andrew SARTORIUS
  • Patent number: 9606818
    Abstract: An apparatus includes a primary hypervisor that is executable on a first set of processors and a secondary hypervisor that is executable on a second set of processors. The primary hypervisor may define settings of a resource and the secondary hypervisor may use the resource based on the settings defined by the primary hypervisor. For example, the primary hypervisor may program memory address translation mappings for the secondary hypervisor. The primary hypervisor and the secondary hypervisor may include their own schedulers.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 28, 2017
    Assignee: Qualcomm Incorporated
    Inventors: Erich James Plondke, Lucian Codrescu, Christopher Edward Koob, Piyush Patel, Thomas Andrew Sartorius
  • Publication number: 20170083333
    Abstract: Systems and methods pertain to a branch target instruction cache (BTIC) of a processor. The BTIC is configured to store one or more branch target instructions at branch target addresses of branch instructions executable by the processor. At least one of the branch target instructions stored in the BTIC is a conditional branch instruction. Branch prediction techniques for predicting the direction of the conditional branch instruction allow one or more instructions following the conditional branch instruction, as well as a branch target address of the conditional branch instruction to also be stored in the BTIC.
    Type: Application
    Filed: September 21, 2015
    Publication date: March 23, 2017
    Inventors: Niket Kumar CHOUDHARY, Michael Scott MCILVAINE, Daren Eugene STREETT, Vimal Kodandarama REDDY, Shekhar Shashi SRIKANTAIAH, Sandeep Suresh NAVADA, Robert Douglas CLANCY, James Norris DIEFFENDERFER, Thomas Andrew SARTORIUS
  • Patent number: 9514061
    Abstract: A memory structure compresses a portion of a memory tag using an indexed tag compression structure. A set of higher order bits of the memory tag may be stored in the indexed tag compression structure, where the set of higher order bits are identified by an index value. A tag array stores a set of lower order bits of the memory tag and the index value identifying the entry in the tag compression structure storing the set of higher order bits of the memory tag. The memory tag may comprise at least a portion of a memory address of a data element stored in a data array.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: December 6, 2016
    Assignee: Qualcomm Incorporated
    Inventors: Henry Arthur Pellerin, III, Thomas Philip Speier, Thomas Andrew Sartorius, Michael William Morrow, James Norris Dieffenderfer, Kenneth Alan Dockser, Michael Scott McIlvaine
  • Publication number: 20160342530
    Abstract: A memory structure compresses a portion of a memory tag using an indexed tag compression structure. A set of higher order bits of the memory tag may be stored in the indexed tag compression structure, where the set of higher order bits are identified by an index value. A tag array stores a set of lower order bits of the memory tag and the index value identifying the entry in the tag compression structure storing the set of higher order bits of the memory tag. The memory tag may comprise at least a portion of a memory address of a data element stored in a data array.
    Type: Application
    Filed: May 20, 2015
    Publication date: November 24, 2016
    Inventors: Henry Arthur PELLERIN, III, Thomas Philip SPEIER, Thomas Andrew SARTORIUS, Michael William MORROW, James Norris DIEFFENDERFER, Kenneth Alan DOCKSER, Michael Scott MCILVAINE
  • Patent number: 9471325
    Abstract: A method and apparatus for allowing an out-of-order processor to reuse an in-use physical register is disclosed herein. The method and apparatus uses identifiers, such as tokens and/or other identifiers in a rename map table (RMT) and a physical register file (PRF), to indicate whether an instruction result is allowed or disallowed to be written into a physical register.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: October 18, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Anil Krishna, Sandeep Suresh Navada, Niket Kumar Choudhary, Michael Scott McIlvaine, Thomas Andrew Sartorius, Rodney Wayne Smith, Kenneth Alan Dockser
  • Patent number: 9436616
    Abstract: A device includes a memory that stores a first page table that includes a first page table entry, wherein the first page table entry further includes a physical address, an alternative location associated with the page table entry, and a physical page of memory associated with the physical address. A first processing unit is configured to: read the first page table entry, and determine the physical address from the first page table entry. The second processing unit is configured to: read the physical address from the first page table entry, determine second page attribute data from the alternative location, wherein the second page attribute data define one or more accessibility attributes of the physical page of memory for the second processing unit, and access the physical page of memory associated with the physical address according to the one or more accessibility attributes.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: September 6, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Colin Christopher Sharp, Thomas Andrew Sartorius
  • Patent number: 9292442
    Abstract: Techniques are described for a multi-processor having two or more processors that increases the opportunity for a load-exclusive command to take a cache line in an Exclusive state, which results in increased performance when a store-exclusive is executed. A new bus operation read prefer exclusive is used as a hint to other caches that a requesting master is likely to store to the cache line, and, if possible, the other cache should give the line up. In most cases, this will result in the other master giving the line up and the requesting master taking the line Exclusive. In most cases, two or more processors are not performing a semaphore management sequence to the same address at the same time. Thus, a requesting master's load-exclusive is able to take a cache line in the Exclusive state an increased number of times.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: March 22, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Philip Speier, Eric F. Robinson, Jaya Prakash Subramaniam Ganasan, Thomas Andrew Sartorius, James Norris Dieffenderfer
  • Patent number: 9092358
    Abstract: Systems and method for memory management units (MMUs) configured to automatically pre-fill a translation lookaside buffer (TLB) with address translation entries expected to be used in the future, thereby reducing TLB miss rate and improving performance. The TLB may be pre-filled with translation entries, wherein addresses corresponding to the pre-fill may be selected based on predictions. Predictions may be derived from external devices, or based on stride values, wherein the stride values may be a predetermined constant or dynamically altered based on access patterns. Pre-filling the TLB may effectively remove latency involved in determining address translations for TLB misses from the critical path.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: July 28, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Bohuslav Rychlik, Thomas Andrew Sartorius, Michael William Morrow, Raymond P. Palma
  • Patent number: 9086813
    Abstract: A wireless mobile device includes a graphic processing unit (GPU) that has a system memory management unit (MMU) for saving and restoring system MMU translation contexts. The system MMU is coupled to a memory and the GPU. The system MMU includes a set of hardware resources. The hardware resources may be context banks, with each of the context banks having a set of hardware registers. The system MMU also includes a hardware controller that is configured to restore a hardware resource associated with an access stream of content issued by an execution thread of the GPU. The associated hardware resource may be restored from the memory into a physical hardware resource when the hardware resource associated with the access stream of content is not stored within one of the hardware resources.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 21, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas M. Zeng, Azzedine Touzni, Thomas Andrew Sartorius
  • Patent number: 9026744
    Abstract: The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. Each of the processors are configured to generate memory access requests to one or more of the memory devices, with each of the memory access requests having an attribute that can be asserted to indicate a strongly-ordered request. The processing system further includes a bus interconnect configured to interface the processors to the memory devices, the bus interconnect being further configured to enforce ordering constraints on the memory access requests based on the attributes.
    Type: Grant
    Filed: October 19, 2005
    Date of Patent: May 5, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Richard Gerard Hofmann, Thomas Andrew Sartorius, Thomas Philip Speier, Jaya Prakash Subramaniam Ganasan, James Norris Dieffenderfer, James Edward Sullivan
  • Patent number: 9026681
    Abstract: A system is disclosed for mapping operating-system-identified addresses for substantially-identical hardware modules into performance-parameter-based addresses for the hardware modules. The mapping is accomplished by configuring a flexible I/O interface responsive to a characterization of at least one performance parameter for each hardware module.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: May 5, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Hee-Jun Park, Alex Kuang-Hsuan Tu, Thomas Andrew Sartorius, Richard Gerard Hofmann, Thomas Andrew Morison
  • Publication number: 20150046604
    Abstract: A system is disclosed for mapping operating-system-identified addresses for substantially-identical hardware modules into performance-parameter-based addresses for the hardware modules. The mapping is accomplished by configuring a flexible I/O interface responsive to a characterization of at least one performance parameter for each hardware module.
    Type: Application
    Filed: August 8, 2013
    Publication date: February 12, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Hee-Jun Park, Alex Kuang-Hsuan Tu, Thomas Andrew Sartorius, Richard Gerard Hofmann, Thomas Andrew Morison
  • Patent number: 8943300
    Abstract: An apparatus for emulating the branch prediction behavior of an explicit subroutine call is disclosed. The apparatus includes a first input which is configured to receive an instruction address and a second input. The second input is configured to receive predecode information which describes the instruction address as being related to an implicit subroutine call to a subroutine. In response to the predecode information, the apparatus also includes an adder configured to add a constant to the instruction address defining a return address, causing the return address to be stored to an explicit subroutine resource, thus, facilitating subsequent branch prediction of a return call instruction.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: January 27, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Brian Michael Stempel, James Norris Dieffenderfer, Thomas Andrew Sartorius, Rodney Wayne Smith
  • Patent number: 8938602
    Abstract: A first processing unit and a second processing unit can access a system memory that stores a common page table that is common to the first processing unit and the second processing unit. The common page table can store virtual memory addresses to physical memory addresses mapping for memory chunks accessed by a job of an application. A page entry, within the common page table, can include a first set of attribute bits that defines accessibility of the memory chunk by the first processing unit, a second set of attribute bits that defines accessibility of the same memory chunk by the second processing unit, and physical address bits that define a physical address of the memory chunk.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: January 20, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Colin Christopher Sharp, Thomas Andrew Sartorius
  • Publication number: 20150019843
    Abstract: A method and apparatus for allowing an out-of-order processor to reuse an in-use physical register is disclosed herein. The method and apparatus uses identifiers, such as tokens and/or other identifiers in a rename map table (RMT) and a physical register file (PRF), to indicate whether an instruction result is allowed or disallowed to be written into a physical register.
    Type: Application
    Filed: November 27, 2013
    Publication date: January 15, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Anil KRISHNA, Sandeep S. NAVADA, Niket K. CHOUDHARY, Michael Scott MCILVAINE, Thomas Andrew SARTORIUS, Rodney Wayne SMITH, Kenneth Alan DOCKSER