Abstract: Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions is disclosed. The processor is configured to support execution of read and/or write instructions that include obsolescence encoding indicating that one or more of its source and/or target register operands are to be obsoleted by the processor. A register encoded as obsolescent means the data value stored in such register will not be used by subsequent instructions in an instruction stream, and thus does not need to be retained. Thus, such register can be set as being in an obsolescent state so that the data value stored in such register can be ignored to improve performance. As one example, data values for registers having an obsolescent state can be ignored and thus not stored in a saved context for a process being switched out, thus conserving memory and improving processing time for a process switch.

Abstract: Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions is disclosed. The processor is configured to support execution of read and/or write instructions that include obsolescence encoding indicating that one or more of its source and/or target register operands are to be obsoleted by the processor. A register encoded as obsolescent means the data value stored in such register will not be used by subsequent instructions in an instruction stream, and thus does not need to be retained. Thus, such register can be set as being in an obsolescent state so that the data value stored in such register can be ignored to improve performance. As one example, data values for registers having an obsolescent state can be ignored and thus not stored in a saved context for a process being switched out, thus conserving memory and improving processing time for a process switch.

Abstract: Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions is disclosed. The processor is configured to support execution of read and/or write instructions that include obsolescence encoding indicating that one or more of its source and/or target register operands are to be obsoleted by the processor. A register encoded as obsolescent means the data value stored in such register will not be used by subsequent instructions in an instruction stream, and thus does not need to be retained. Thus, such register can be set as being in an obsolescent state so that the data value stored in such register can be ignored to improve performance. As one example, data values for registers having an obsolescent state can be ignored and thus not stored in a saved context for a process being switched out, thus conserving memory and improving processing time for a process switch.

Abstract: Providing exception stack management using stack panic fault exceptions in processor-based devices is disclosed. In this regard, a processor device defines a “stack panic fault exception” that may be raised upon execution of an exception handler store operation attempting to write state data into an exception stack, and provides a dedicated plurality of stack panic fault exception state registers in which stack panic fault exception state data may be saved. Upon detecting a first exception, the processor device transfers program control to an exception handler for the first exception. If a second exception occurs upon execution of a store operation in the exception handler, the processor device determines that the second exception should be handled as a stack panic fault exception, saves the stack panic fault exception state data in the stack panic fault exception state registers, and transfers program control to a stack panic fault exception handler.

Abstract: Providing exception stack management using stack panic fault exceptions in processor-based devices is disclosed. In this regard, a processor device defines a “stack panic fault exception” that may be raised upon execution of an exception handler store operation attempting to write state data into an exception stack, and provides a dedicated plurality of stack panic fault exception state registers in which stack panic fault exception state data may be saved. Upon detecting a first exception, the processor device transfers program control to an exception handler for the first exception. If a second exception occurs upon execution of a store operation in the exception handler, the processor device determines that the second exception should be handled as a stack panic fault exception, saves the stack panic fault exception state data in the stack panic fault exception state registers, and transfers program control to a stack panic fault exception handler.

Abstract: Providing express memory obsolescence in processor-based devices is disclosed. In this regard, an instruction set architecture (ISA) of a processor-based device provides a memory load instruction indicating a final memory load operation from a memory address (i.e., after the memory load operation represented by the memory load instruction is performed, the value at the memory address need not be maintained). Upon receiving the memory load instruction by an execution pipeline of the processor-based device, an entry corresponding to the memory address of the memory load instruction is located in an intermediate memory external to the system memory of the processor-based device, and used to perform the final memory load operation. After the final memory load operation is performed using the entry, a value of an obsolete indicator for the entry is set to indicate that the entry can be reused prior to its contents being written to the system memory.

Abstract: Providing express memory obsolescence in processor-based devices is disclosed. In this regard, an instruction set architecture (ISA) of a processor-based device provides a memory load instruction indicating a final memory load operation from a memory address (i.e., after the memory load operation represented by the memory load instruction is performed, the value at the memory address need not be maintained). Upon receiving the memory load instruction by an execution pipeline of the processor-based device, an entry corresponding to the memory address of the memory load instruction is located in an intermediate memory external to the system memory of the processor-based device, and used to perform the final memory load operation. After the final memory load operation is performed using the entry, a value of an obsolete indicator for the entry is set to indicate that the entry can be reused prior to its contents being written to the system memory.

Abstract: Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions is disclosed. The processor is configured to support execution of read and/or write instructions that include obsolescence encoding indicating that one or more of its source and/or target register operands are to be obsoleted by the processor. A register encoded as obsolescent means the data value stored in such register will not be used by subsequent instructions in an instruction stream, and thus does not need to be retained. Thus, such register can be set as being in an obsolescent state so that the data value stored in such register can be ignored to improve performance. As one example, data values for registers having an obsolescent state can be ignored and thus not stored in a saved context for a process being switched out, thus conserving memory and improving processing time for a process switch.

Abstract: A method includes reading, by a processor, one or more configuration values from a storage device or a memory management unit. The method also includes loading the one or more configuration values into one or more registers of the processor. The one or more registers are useable by the processor to perform address translation.

Abstract: Systems and methods are directed to prefetch mechanisms involving non-equal magnitude stride values. A non-equal magnitude functional relationship between successive stride values, may be detected, wherein the stride values are based on distances between target addresses of successive load instructions. At least a next stride value for prefetching data, may be determined, wherein the next stride value is based on the non-equal magnitude functional relationship and a previous stride value. Data prefetch may be from at least one prefetch address calculated based on the next stride value and a previous target address. The non-equal magnitude functional relationship may include a logarithmic relationship corresponding to a binary search algorithm.

Abstract: Systems and methods for managing access to a cache relate to determining one or more execute permissions associated with a write-address of a write-request to the cache. The cache may be a unified cache for storing data as well as instructions. If there is a write-miss in the cache for the write-request, a cache controller may determine whether to implement a write-allocate policy or a write-no-allocate policy for servicing the write-miss, based on the one or more execute permissions. The one or more execute permissions can relate to a privilege level associated with the write-address. Execute permissions of a producing agent which generated the write-request and an execute permission of a consuming agent which can execute from the write-address may be based on the privilege levels of the producing agent and the consuming agent, respectively.

Abstract: Delays due to waiting for operands that will not be used by a select operand instruction, are alleviated based on an early recognition that such operand data is not required in order to complete the processing of the select operand instruction. At appropriate points prior to execution, determinations are made regarding a selection criterion or criteria specified by the select operand instruction, conditions that affect the selection criteria, and the availability of operands. A hold circuit uses the determinations to control the activation and release of a hold signal that controls processor pipeline stalls. A stall required to wait for operand data is skipped or a stall is terminated early, if the selected operand is available even though the other operand, that will not be used, is not available. A stall due to waiting for operands is maintained until the selection criteria is met and the selected operand is fetched and made available.

Abstract: A cache fill line is received, including an index, a thread identifier, and cache fill line data. The cache is probed, using the index and a different thread identifier, for a potential duplicate cache line. The potential duplicate cache line includes cache line data and the different thread identifier. Upon the cache fill line data matching the cache line data, duplication is identified. The potential duplicate cache line is set as a shared resident cache line, and the thread share permission tag is set to a permission state.

Abstract: An apparatus includes a primary hypervisor that is executable on a first set of processors and a secondary hypervisor that is executable on a second set of processors. The primary hypervisor may define settings of a resource and the secondary hypervisor may use the resource based on the settings defined by the primary hypervisor. For example, the primary hypervisor may program memory address translation mappings for the secondary hypervisor. The primary hypervisor and the secondary hypervisor may include their own schedulers.

Abstract: Systems and methods pertain to a branch target instruction cache (BTIC) of a processor. The BTIC is configured to store one or more branch target instructions at branch target addresses of branch instructions executable by the processor. At least one of the branch target instructions stored in the BTIC is a conditional branch instruction. Branch prediction techniques for predicting the direction of the conditional branch instruction allow one or more instructions following the conditional branch instruction, as well as a branch target address of the conditional branch instruction to also be stored in the BTIC.

Abstract: A memory structure compresses a portion of a memory tag using an indexed tag compression structure. A set of higher order bits of the memory tag may be stored in the indexed tag compression structure, where the set of higher order bits are identified by an index value. A tag array stores a set of lower order bits of the memory tag and the index value identifying the entry in the tag compression structure storing the set of higher order bits of the memory tag. The memory tag may comprise at least a portion of a memory address of a data element stored in a data array.

Abstract: A memory structure compresses a portion of a memory tag using an indexed tag compression structure. A set of higher order bits of the memory tag may be stored in the indexed tag compression structure, where the set of higher order bits are identified by an index value. A tag array stores a set of lower order bits of the memory tag and the index value identifying the entry in the tag compression structure storing the set of higher order bits of the memory tag. The memory tag may comprise at least a portion of a memory address of a data element stored in a data array.

Abstract: A method and apparatus for allowing an out-of-order processor to reuse an in-use physical register is disclosed herein. The method and apparatus uses identifiers, such as tokens and/or other identifiers in a rename map table (RMT) and a physical register file (PRF), to indicate whether an instruction result is allowed or disallowed to be written into a physical register.

Abstract: A device includes a memory that stores a first page table that includes a first page table entry, wherein the first page table entry further includes a physical address, an alternative location associated with the page table entry, and a physical page of memory associated with the physical address. A first processing unit is configured to: read the first page table entry, and determine the physical address from the first page table entry. The second processing unit is configured to: read the physical address from the first page table entry, determine second page attribute data from the alternative location, wherein the second page attribute data define one or more accessibility attributes of the physical page of memory for the second processing unit, and access the physical page of memory associated with the physical address according to the one or more accessibility attributes.

Abstract: Techniques are described for a multi-processor having two or more processors that increases the opportunity for a load-exclusive command to take a cache line in an Exclusive state, which results in increased performance when a store-exclusive is executed. A new bus operation read prefer exclusive is used as a hint to other caches that a requesting master is likely to store to the cache line, and, if possible, the other cache should give the line up. In most cases, this will result in the other master giving the line up and the requesting master taking the line Exclusive. In most cases, two or more processors are not performing a semaphore management sequence to the same address at the same time. Thus, a requesting master's load-exclusive is able to take a cache line in the Exclusive state an increased number of times.