Patents by Inventor Thomas Anthony Gregg
Thomas Anthony Gregg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7979548Abstract: A method and system are disclosed for logically partitioning resources of a single channel adapter for use in a system area network. Each resource includes a partition identifier register within which is stored a partition identifier. A first one of the resources is assigned to a first partition by storing a first partition identifier in the partition identifier register within the first one of the resources. A second one of the resources is assigned to a second partition by storing a second partition identifier in the partition identifier register within the second one of the resources. Partitioning of the resources is enforced by permitting access to the first resource by only the first partition and permitting access to the second resource by only the second partition by checking the partition identifiers of each resource.Type: GrantFiled: September 30, 2003Date of Patent: July 12, 2011Assignee: International Business Machines CorporationInventors: Richard Louis Arndt, Bruce Leroy Beukema, David F. Craddock, Ronald Edward Fuhs, Thomas Anthony Gregg, Donald William Schmidt, Bruce Marshall Walk
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Patent number: 7873751Abstract: A method, computer program product, and data processing system for providing system-area network (SAN) multicasting functionality in a logically partitioned (LPAR) data processing system in which a channel adapter is shared among a plurality of logical partitions is disclosed. A preferred embodiment of the present invention allows LPAR “hypervisor” firmware to assume the responsibility for multicast protocol handling and distribution of packets among logical partitions.Type: GrantFiled: July 2, 2008Date of Patent: January 18, 2011Assignee: International Business Machines CorporationInventors: Richard Louis Arndt, Bruce Leroy Beukema, David F. Craddock, Ronald Edward Fuhs, Thomas Anthony Gregg, Calvin Charles Paynton, Steven L. Rogers, Donald William Schmidt, Bruce Marshall Walk
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Patent number: 7574537Abstract: A method, apparatus, and computer program product are disclosed in a data processing system for migrating data pages subject to DMA access by temporarily disabling selected DMA operations within a physical I/O adapter. A determination is made as to whether to disable data access DMA capabilities of the physical I/O adapter. An operating mode of the physical I/O adapter is set to a particular mode utilizing a mode bit according to the determination of whether to disable data access DMA capabilities. Only data access DMA capabilities of the physical I/O adapter are disabled when the mode bit is set. Administrative services operations continue to be performed by the physical I/O adapter when the data access DMA capabilities of the physical I/O adapter are disabled.Type: GrantFiled: February 3, 2005Date of Patent: August 11, 2009Assignee: International Business Machines CorporationInventors: Richard Louis Arndt, David F. Craddock, Thomas Anthony Gregg, Donald William Schmidt
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Patent number: 7555002Abstract: An aliased queue pair is provided within a logically partitioned data processing system for each logical partition for the single general services management queue pair that exists within a physical host channel adapter. Packets intended for the logical ports are received at the physical port. Multiple partitions exist within the data processing system. When one of these partitions needs to use one of the logical ports, a queue pair is selected. The queue pair is then associated with the logical port. The queue pair is configured as an aliased general services management queue pair and is used by the partition as if the aliased queue pair were the single general services management queue pair provided in the channel adapter.Type: GrantFiled: November 6, 2003Date of Patent: June 30, 2009Assignee: International Business Machines CorporationInventors: Richard Louis Arndt, Bruce Leroy Beukema, David F. Craddock, Ronald Edward Fuhs, Thomas Anthony Gregg, Calvin Charles Paynton, Steven L. Rogers, Donald William Schmidt, Bruce Marshall Walk
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Publication number: 20080267183Abstract: A method, computer program product, and data processing system for providing system-area network (SAN) multicasting functionality in a logically partitioned (LPAR) data processing system in which a channel adapter is shared among a plurality of logical partitions is disclosed. A preferred embodiment of the present invention allows LPAR “hypervisor” firmware to assume the responsibility for multicast protocol handling and distribution of packets among logical partitions.Type: ApplicationFiled: July 2, 2008Publication date: October 30, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Richard Louis Arndt, Bruce Leroy Beukema, David F. Craddock, Ronald Edward Fuhs, Thomas Anthony Gregg, Calvin Charles Paynton, Steven L. Rogers, Donald William Schmidt, Bruce Marshall Walk
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Patent number: 7428598Abstract: A method, computer program product, and data processing system for providing system-area network (SAN) multicasting functionality in a logically partitioned (LPAR) data processing system in which a channel adapter is shared among a plurality of logical partitions is disclosed. A preferred embodiment of the present invention allows LPAR “hypervisor” firmware to assume the responsibility for multicast protocol handling and distribution of packets among logical partitions.Type: GrantFiled: November 20, 2003Date of Patent: September 23, 2008Assignee: International Business Machines CorporationInventors: Richard Louis Arndt, Bruce Leroy Beukema, David F. Craddock, Ronald Edward Fuhs, Thomas Anthony Gregg, Calvin Charles Paynton, Steven L. Rogers, Donald William Schmidt, Bruce Marshall Walk
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Patent number: 7283473Abstract: An apparatus, system and method for providing multiple logical partitions in a system area network are provided Logical partitioning support is provided for host channel adapters which allows multiple operating systems to share the resources of a single physical host channel adapter (HCA). The apparatus, system and method ensures that each operating system is unaware that the HCA hardware resources are being shared with other operating systems and further guarantees that the individual operating systems are prevented from accessing HCA hardware resources which are associated with other operating systems.Type: GrantFiled: April 10, 2003Date of Patent: October 16, 2007Assignee: International Business Machines CorporationInventors: Richard Louis Arndt, Bruce Leroy Beukema, David F. Craddock, Ronald Edward Fuhs, Thomas Anthony Gregg, Allan Samuel Meritt, Calvin Charles Paynton, Steven L. Rogers, Donald William Schmidt, Bruce Marshall Walk
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Patent number: 7149220Abstract: A method, system, and product in a data processing system are disclosed for managing data transmitted from a first end node to a second end node included in the data processing system. A logical connection is established between the first end node and the second end node prior to transmitting data between the end nodes. An instance number is associated with this particular logical connection. The instance number is included in each packet transmitted between the end nodes while this logical connection remains established. The instance number remains constant during this logical connection. The instance number is altered, such as by incrementing it, each time a logical connection between these end nodes is reestablished. Thus, each packet is associated with a particular instance of the logical connection. When a packet is received, the instance number included in the packet may be used to determine whether the packet is a stale packet transmitted during a previous logical connection between these end nodes.Type: GrantFiled: April 25, 2002Date of Patent: December 12, 2006Assignee: International Business Machines CorporationInventors: Bruce Leroy Beukema, Thomas Anthony Gregg, Danny Marvin Neal, Renato John Recio
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Patent number: 7099955Abstract: A method for routing System Area Network (SAN) packets to multiple partitions within a single end node is provided. A range of Local Identification addresses (LIDs) are assigned to a channel adapter port within the SAN. Lower order bits within the LID are then assigned to select the particular partition in the end node. The Local ID Mask Control (LMC) field is used to assign multiple LIDs to a single port, using those low order bits to then route the message to the appropriate partition in the end node.Type: GrantFiled: October 19, 2000Date of Patent: August 29, 2006Assignee: International Business Machines CorporationInventors: Thomas Anthony Gregg, Gregory Francis Pfister, Renato John Recio, Steven Mark Thurber
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Patent number: 7092401Abstract: An apparatus and method for managing reliable datagram work queues, and associated completion queues, using head and tail pointers with end-to-end context error cache are provided. Reliable datagram (RD) queue head and tail pointers are maintained in the channel interface and the host channel adapter. The head and tail pointers in the host channel adapter include a RD queue page table index and a RD queue page index for identifying a position within the RD queue. For RD work queues, in the channel interface, the tail pointer is used to identify a next position where a work queue entry may be written and the head pointer is used only to determine whether the work queue is full. In the host channel adapter, the head pointer is used to identify a next work queue entry for processing and the tail pointer is used to determine if the queue is empty.Type: GrantFiled: November 15, 2001Date of Patent: August 15, 2006Assignee: International Business Machines CorporationInventors: David F. Craddock, Thomas Anthony Gregg, Ian David Judd, Gregory Francis Pfister, Renato John Recio
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Patent number: 7093024Abstract: A mechanism for allowing a single physical IB node to virtualize a plurality of host channel adapters is provided. This includes providing the appearance of both a router and multiple virtual HCA's residing behind that router, to the external REAL subnet components. Each virtual host channel adapter will have unique access control levels. One or more InfiniBand subnets are virtualized in such a way that nodes residing both within the virtual subnets and in separate physical subnets are completely unaware of the virtualization. This virtualization of InfiniBand subnets significantly increases the horizontal scaling capabilities of a single InfiniBand physical component, while at the same time provides “native” network throughput for all the virtual hosts.Type: GrantFiled: September 27, 2001Date of Patent: August 15, 2006Assignee: International Business Machines CorporationInventors: David F. Craddock, David Arlen Elko, Thomas Anthony Gregg, Gregory Francis Pfister, Renato John Recio, Donald William Schmidt
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Patent number: 7010633Abstract: An apparatus, system and method for controlling access to facilities based on usage class of a requestor are provided. With the apparatus, system and method, a two level protection mechanism is provided for protecting host channel adapter (HCA) facilities from unauthorized access. With the present invention, a first level of access is provided through virtual address translation and a mechanism for determining if the requestor of access may access a system memory address space page associated with a real address to which the virtual address maps. A second level of access is provided through the allocation of usage classes and determining a required usage class for accessing an HCA facility.Type: GrantFiled: April 10, 2003Date of Patent: March 7, 2006Assignee: International Business Machines CorporationInventors: Richard Louis Arndt, Bruce Leroy Beukema, David F. Craddock, Ronald Edward Fuhs, Thomas Anthony Gregg, Bruce Marshall Walk
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Patent number: 6938138Abstract: A method and apparatus for accessing a memory. Access rights for a memory operation are verified using a first data structure in response to receiving a request to perform the operation, wherein the request includes a virtual address for the operation. Responsive to access rights being verified for the memory operation, the virtual address translated into a real address using a second data structure.Type: GrantFiled: January 11, 2001Date of Patent: August 30, 2005Assignee: International Business Machines CorporationInventors: Bruce Leroy Beukema, David Craddock, Ronald Edward Fuhs, Thomas Anthony Gregg, Gregory Francis Pfister, Renato John Recio, Steven L. Rogers
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Patent number: 6834332Abstract: An apparatus and method for swapping out real memory by inhibiting input/output (I/O) operations to a memory region are provided. The apparatus and method provide a mechanism in which a quiesce indicator is provided in a field containing the current outstanding I/O count associated with the memory region whose real memory is to be swapped out. The current I/O field and the quiesce indicator are used as a means for communicating between a shared resource arbitrator and a guest consumer. When the quiesce indicator is set, the guest consumer is informed that it should not send any further I/O operations to that memory region. When the number of pending I/O operations against the memory region is zero, a valid bit in a protection table is set to invalid, and the real memory associated with the memory region may be swapped out.Type: GrantFiled: August 30, 2001Date of Patent: December 21, 2004Assignee: International Business Machines CorporationInventors: David F. Craddock, Thomas Anthony Gregg, Renato John Recio, Donald William Schmidt
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Publication number: 20040202189Abstract: An apparatus, system and method for providing multiple logical partitions in a system area network are provided Logical partitioning support is provided for host channel adapters which allows multiple operating systems to share the resources of a single physical host channel adapter (HCA). The apparatus, system and method ensures that each operating system is unaware that the HCA hardware resources are being shared with other operating systems and further guarantees that the individual operating systems are prevented from accessing HCA hardware resources which are associated with other operating systems.Type: ApplicationFiled: April 10, 2003Publication date: October 14, 2004Applicant: International Business Machines CorporationInventors: Richard Louis Arndt, Bruce Leroy Beukema, David F. Craddock, Ronald Edward Fuhs, Thomas Anthony Gregg, Allan Samuel Meritt, Calvin Charles Paynton, Steven L. Rogers, Donald William Schmidt, Bruce Marshall Walk
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Publication number: 20040205253Abstract: An apparatus, system and method for controlling access to facilities based on usage class of a requestor are provided. With the apparatus, system and method, a two level protection mechanism is provided for protecting host channel adapter (HCA) facilities from unauthorized access. With the present invention, a first level of access is provided through virtual address translation and a mechanism for determining if the requestor of access may access a system memory address space page associated with a real address to which the virtual address maps. A second level of access is provided through the allocation of usage classes and determining a required usage class for accessing an HCA facility.Type: ApplicationFiled: April 10, 2003Publication date: October 14, 2004Applicant: International Business Machines CorporationInventors: Richard Louis Arndt, Bruce Leroy Beukema, David F. Craddock, Ronald Edward Fuhs, Thomas Anthony Gregg, Bruce Marshall Walk
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Patent number: 6789143Abstract: A distributed computing system having (host and I/O) end nodes, switches, routers, and links interconnecting these components is provided. The end nodes use send and receive queue pairs to transmit and receive messages. The end nodes use completion queues to inform the end user when a message has been completely sent or received and whether an error occurred during the message transmission or reception process. A mechanism implements these queue pairs and completion queues in hardware. A mechanism for controlling the transfer of work requests from the consumer to the CA hardware and work completions from the CA hardware to the consumer using head and tail pointers that reference circular buffers is also provided. The QPs and CQs do not contain Work Queue Entries and Completion Queue Entries respectively, but instead contain references to these entries.Type: GrantFiled: September 24, 2001Date of Patent: September 7, 2004Assignee: International Business Machines CorporationInventors: David F. Craddock, Thomas Anthony Gregg, Ian David Judd, Gregory Francis Pfister, Renato John Recio, Donald William Schmidt
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Patent number: 6748499Abstract: A method, computer program product, and data processing system for sharing memory protection tables and address translation tables among multiple Host Channel Adapters are disclosed. The protection and address translation tables for a shared memory region are written in memory of the host. The Host Channel Adapters are registered with the memory region so that each adapter stores an address pointer to the tables. In this way, the tables need not be duplicated for each adapter.Type: GrantFiled: November 15, 2001Date of Patent: June 8, 2004Assignee: International Business Machines CorporationInventors: Bruce Leroy Beukema, David F. Craddock, Thomas Anthony Gregg, Renato John Recio
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Patent number: 6725296Abstract: An apparatus and method for managing work and completion queues using head and tail circular pointers. With the apparatus and method, queue head and tail pointers are maintained in the channel interface and the host channel adapter. The head and tail pointers in the host channel adapter include a queue pointer table index and a queue page index for identifying a position within the queue. For work queues, the tail pointer in the channel interface is used to identify a next position where a work queue entry may be written. The head pointer in the channel interface is used only to determine whether the work queue is full or not. The head pointer in the host channel adapter is used to identify a next work queue entry for processing by the host channel adapter. The tail pointer in the host channel adapter is used by the host channel adapter to determine if the queue is empty. For completion queues, the head pointer in the channel interface is used to identify a next completion queue entry to be processed.Type: GrantFiled: July 26, 2001Date of Patent: April 20, 2004Assignee: International Business Machines CorporationInventors: David F. Craddock, Thomas Anthony Gregg, Ian David Judd, Gregory Francis Pfister, Renato John Recio, Donald William Schmidt
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Patent number: 6721335Abstract: Defines and handles segments in messages to place pauses and interruptions within the communication of a message between transmitted segments of the message. A common link switch is used in a network to connect links to all nodes, the segment structures in each message is preserved when packets of each message are passed within the switch to a switch transmitter connected to the destination node indicated in each packet of the message for transmitting each of the message segments. Each transmitter stores the source identifier of the first packet it transmits for a segment and then gives priority to transmitting packets which contain source and destination identifiers which match the current transmitter stored source identifier and match the destination node connected to the transmitter. This priority enables each switch transmitter to interleaves segments of concurrent messages while preserving the segmentation of transmitted packets to maintaining a maximum network communication rate for the messages.Type: GrantFiled: November 12, 1999Date of Patent: April 13, 2004Assignee: International Business Machines CorporationInventor: Thomas Anthony Gregg