Patents by Inventor Thomas Aquinas Repucci

Thomas Aquinas Repucci has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Edge generator-based phase locked loop reference clock generator for automated test system
    Patent number: 9397670
    Abstract: An automatic test system configured for generating a periodic signal of a programmable frequency. The automatic test system may comprise a clock, an edge generator coupled to the clock, a phase locked loop, and a delay adjustment circuit. The edge generator may comprise an edge generator output, an enable input and a delay input. The edge generator may produce at the edge generator output a signal with a delay relative to an edge of the clock specified by a value at the delay input in each cycle of the clock for which the enable input is asserted. The phase locked loop may comprise a reference input and a phase locked loop output configured to provide the periodic signal of the programmable frequency. The delay adjustment circuit may comprise an accumulator that may increase in value by a programmed amount for each cycle of the clock.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: July 19, 2016
    Assignee: Teradyne, Inc.
    Inventors: Jan Paul Anthonie van der Wagt, Jeffrey Wade Sanders, Thomas Aquinas Repucci, Ronald A. Sartschev
  • Edge Generator-Based Phase Locked Loop Reference Clock Generator for Automated Test System
    Publication number: 20160006441
    Abstract: An automatic test system configured for generating a periodic signal of a programmable frequency. The automatic test system may comprise a clock, an edge generator coupled to the clock, a phase locked loop, and a delay adjustment circuit. The edge generator may comprise an edge generator output, an enable input and a delay input. The edge generator may produce at the edge generator output a signal with a delay relative to an edge of the clock specified by a value at the delay input in each cycle of the clock for which the enable input is asserted. The phase locked loop may comprise a reference input and a phase locked loop output configured to provide the periodic signal of the programmable frequency. The delay adjustment circuit may comprise an accumulator that may increase in value by a programmed amount for each cycle of the clock.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 7, 2016
    Applicant: Teradyne, Inc.
    Inventors: Jan Paul Anthonie van der Wagt, Jeffrey Wade Sanders, Thomas Aquinas Repucci, Ronald A. Sartschev