Abstract: A method and apparatus that allow packet based communication transactions between devices over an interconnect bus to be captured to measure performance. Performance metrics may be determined by capturing events at various locations as they pass through the system. Performance may be verified at run time by computing performance metrics for captured events and comparing such metrics to predefined performance ranges and/or self learned performance ranges. Furthermore, embodiments of the present invention provide for dynamic tailoring of bus traffic to generate potential failing conditions. For some embodiments, performance verification as described herein may be performed in a simulation environment.

Abstract: A method and apparatus that allow packet based communication transactions between devices over an interconnect bus to be captured to measure performance. Performance metrics may be determined by capturing events at various locations as they pass through the system. Performance may be verified at run time by computing performance metrics for captured events and comparing such metrics to predefined performance ranges and/or self learned performance ranges. Furthermore, embodiments of the present invention provide for dynamic tailoring of bus traffic to generate potential failing conditions. For some embodiments, performance verification as described herein may be performed in a simulation environment.

Abstract: Methods, apparatus, and articles of manufacture that allow packet-based communication transactions between devices over an interconnect bus to be captured in a standardized format are provided. The standardized format may enable the display of the bus transactions via a graphical user interface (GUI), which may greatly facilitate viewing and analyzing the transactions when validating communications.

Abstract: A simulation system includes glitch injection circuitry in one or more hardware design units to allow the injection of glitches or noise to evaluate the system's response to errors on signals between the hardware design units. The simulation system includes a stimulation module with a set of drivers to input simulation patterns into the design units. Some inputs to software models are driven by the outputs of software models of another design unit. The stimulation module can monitor these signals driven by the software model but it is difficult for the stimulation module to directly drive these signals. The added glitch circuitry allows injection of errors into the simulated hardware by the stimulation module on signals that are not directly driven by the stimulation module but are driven by the outputs of hardware design units.