Abstract: Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic region while recessed access devices (RADs) are provided in an array region for a memory device. During gate stack patterning in the periphery, word lines are recessed within the trenches for the array RADs. Side wall spacer formation in the periphery simultaneously provides an insulating cap layer burying the word lines within the trenches of the array.

Abstract: This invention includes methods of forming openings into dielectric material. In one implementation, an opening is partially etched through dielectric material, with such opening comprising a lowest point and opposing sidewalls of the dielectric material. At least respective portions of the opposing sidewalls within the opening are lined with an electrically conductive material. With such electrically conductive material over said respective portions within the opening, plasma etching is conducted into and through the lowest point of the dielectric material of the opening to extend the opening deeper within the dielectric material. Other aspects and implementations are contemplated.

Abstract: The invention includes methods of forming devices associated with semiconductor constructions. In exemplary methods, common processing steps are utilized to form fully silicided recessed array access gates and partially silicided periphery transistor gates.

Abstract: Capacitors and methods of forming capacitors are described. According to one implementation, a capacitor opening is formed over a substrate node location. Electrically conductive material is subsequently formed within the capacitor opening and makes an electrical connection with the node location. A protuberant insulative structure is formed within the capacitor opening and includes a lateral outer surface at least a portion of which is supported by and extends elevationally below adjacent conductive material. First and second capacitor plates and a dielectric layer therebetween are formed within the capacitor opening and supported by the protuberant structure. In one aspect, the conductive material is formed to occupy less than all of the capacitor opening and to leave a void therewithin, with the protuberant structure substantially, if not completely filling in the void.

Abstract: Capacitors and methods of forming capacitors are described. According to one implementation, a capacitor opening is formed over a substrate node location. Electrically conductive material is subsequently formed within the capacitor opening and makes an electrical connection with the node location. A protuberant insulative structure is formed within the capacitor opening and includes a lateral outer surface at least a portion of which is supported by and extends elevationally below adjacent conductive material. First and second capacitor plates and a dielectric layer therebetween are formed within the capacitor opening and supported by the protuberant structure. In one aspect, the conductive material is formed to occupy less than all of the capacitor opening and to leave a void therewithin, with the protuberant structure substantially, if not completely filling in the void.

Abstract: A method for forming a contact intermediate adjacent electrical components including, providing a node to which electrical connections are desired and which is located between two electrical components; providing oxidation conditions effective to grow an oxide cap on the outer portions of each of the adjacent electric components; exposing a given target area between the adjacent electrical components, the given target area being larger than what would otherwise exist if the oxide caps are not present; selectively removing material from within the target area while simultaneously protecting the adjacent electrical components from the selective removal conditions; selectively removing material from the target area thereby exposing the underlying node; and providing an electrically conductive material within the target area and which is disposed in electrical contact with the node.

Abstract: Capacitors and methods of forming capacitors are described. According to one implementation, a capacitor opening is formed over a substrate node location. Electrically conductive material is subsequently formed within the capacitor opening and makes an electrical connection with the node location. A protuberant insulative structure is formed within the capacitor opening and includes a lateral outer surface at least a portion of which is supported by and extends elevationally below adjacent conductive material. First and second capacitor plates and a dielectric layer therebetween are formed within the capacitor opening and supported by the protuberant structure. In one aspect, the conductive material is formed to occupy less than all of the capacitor opening and to leave a void therewithin, with the protuberant structure substantially, if not completely filling in the void.

Abstract: A method for forming a contact intermediate adjacent electrical components including, providing a node to which electrical connections are desired and which is located between two electrical components; providing oxidation conditions effective to grow an oxide cap on the outer portions of each of the adjacent electric components; exposing a given target area between the adjacent electrical components, the given target area being larger than what would otherwise exist if the oxide caps are not present; selectively removing material from within the target area while simultaneously protecting the adjacent electrical components from the selective removal conditions; selectively removing material from the target area thereby exposing the underlying node; and providing an electrically conductive material within the target area and which is disposed in electrical contact with the node.