Abstract: According to the present invention, clock control logic circuitry of a clocked memory device using precharged data path techniques generates a self-timed pulse. The self-timed pulse is representative of a pulsed path active strobe or a reset strobe of the clocked memory device. The clock control logic circuitry of the present invention is characterized as having at least a first delay timing chain, a second delay timing chain, and means for selectively changing the width of a self-timed pulse generated by the clock control logic circuitry. Selectively changing the width of the self-timed pulse is accomplished by selectively adding the delay of the first delay timing chain to the delay of the second delay timing chain during a special mode of operation of the clocked memory device.