Patents by Inventor Thomas Ayers
Thomas Ayers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10865737Abstract: A system and method for an improved thrust reverser is provided. The provided thrust reverser employs hidden linkage assemblies to decrease drag in the engine exhaust flow and increase turbine engine performance. The hidden linkage assemblies are placed in a space between the blocker door and the transcowl, thereby not affecting the engine exhaust flow.Type: GrantFiled: August 29, 2017Date of Patent: December 15, 2020Assignee: HONEYWELL INTERNATIONAL INC.Inventors: Danis Burton Smith, Alexandre Guerinot, Remo Neri, James Thomas Ayers, III
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Patent number: 10659714Abstract: An image sensor including a pixel circuit and an active reset circuit. The pixel circuit includes a light sensing element, a storage node selectively connected to the light sensing element, an output transistor configured to, during a readout operation, output a signal that is based on a potential of the charge storage node to an output line, and a selection transistor that controls the readout operation. The active reset circuit includes a first current path and a second current path, the first current path extending from a power supply node to the output line via the selection transistor and the output transistor, and the second current path extending from the power supply node to the output line via a first transistor and a second transistor. The active reset circuit is configured to, when the selection transistor and the first transistor are both ON, set a potential of the charge storage node based on a potential of a gate of the second transistor.Type: GrantFiled: October 1, 2018Date of Patent: May 19, 2020Assignee: Sony CorporationInventors: Thomas Ayers, Jinsuk Kang, Brian Carey, Noam Eshel, Frederick Brady
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Publication number: 20190089918Abstract: An image sensor including a pixel circuit and an active reset circuit. The pixel circuit includes a light sensing element, a storage node selectively connected to the light sensing element, an output transistor configured to, during a readout operation, output a signal that is based on a potential of the charge storage node to an output line, and a selection transistor that controls the readout operation. The active reset circuit includes a first current path and a second current path, the first current path extending from a power supply node to the output line via the selection transistor and the output transistor, and the second current path extending from the power supply node to the output line via a first transistor and a second transistor. The active reset circuit is configured to, when the selection transistor and the first transistor are both ON, set a potential of the charge storage node based on a potential of a gate of the second transistor.Type: ApplicationFiled: October 1, 2018Publication date: March 21, 2019Inventors: Thomas Ayers, Jinsuk Kang, Brian Carey, Noam Eshel, Frederick Brady
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Publication number: 20190063367Abstract: A system and method for an improved thrust reverser is provided. The provided thrust reverser employs hidden linkage assemblies to decrease drag in the engine exhaust flow and increase turbine engine performance. The hidden linkage assemblies are placed in a space between the blocker door and the transcowl, thereby not affecting the engine exhaust flow.Type: ApplicationFiled: August 29, 2017Publication date: February 28, 2019Applicant: HONEYWELL INTERNATIONAL INC.Inventors: Danis Burton Smith, Alexandre Guerinot, Remo Neri, James Thomas Ayers, III
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Patent number: 10110841Abstract: An image sensor including a pixel circuit and an active reset circuit. The pixel circuit includes a light sensing element, a storage node selectively connected to the light sensing element, an output transistor configured to, during a readout operation, output a signal that is based on a potential of the charge storage node to an output line, and a selection transistor that controls the readout operation. The active reset circuit includes a first current path and a second current path, the first current path extending from a power supply node to the output line via the selection transistor and the output transistor, and the second current path extending from the power supply node to the output line via a first transistor and a second transistor. The active reset circuit is configured to, when the selection transistor and the first transistor are both ON, set a potential of the charge storage node based on a potential of a gate of the second transistor.Type: GrantFiled: June 8, 2017Date of Patent: October 23, 2018Assignee: Sony CorporationInventors: Thomas Ayers, Jinsuk Kang, Brian Carey, Noam Eshel, Frederick Brady
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Publication number: 20170280084Abstract: An image sensor including a pixel circuit and an active reset circuit. The pixel circuit includes a light sensing element, a storage node selectively connected to the light sensing element, an output transistor configured to, during a readout operation, output a signal that is based on a potential of the charge storage node to an output line, and a selection transistor that controls the readout operation. The active reset circuit includes a first current path and a second current path, the first current path extending from a power supply node to the output line via the selection transistor and the output transistor, and the second current path extending from the power supply node to the output line via a first transistor and a second transistor. The active reset circuit is configured to, when the selection transistor and the first transistor are both ON, set a potential of the charge storage node based on a potential of a gate of the second transistor.Type: ApplicationFiled: June 8, 2017Publication date: September 28, 2017Inventors: Thomas Ayers, Jinsuk Kang, Brian Carey, Noam Eshel, Frederick Brady
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Patent number: 9736413Abstract: An image sensor including a pixel circuit and an active reset circuit. The pixel circuit includes a light sensing element, a storage node selectively connected to the light sensing element, an output transistor configured to, during a readout operation, output a signal that is based on a potential of the charge storage node to an output line, and a selection transistor that controls the readout operation. The active reset circuit includes a first current path and a second current path, the first current path extending from a power supply node to the output line via the selection transistor and the output transistor, and the second current path extending from the power supply node to the output line via a first transistor and a second transistor. The active reset circuit is configured to, when the selection transistor and the first transistor are both ON, set a potential of the charge storage node based on a potential of a gate of the second transistor.Type: GrantFiled: February 3, 2016Date of Patent: August 15, 2017Assignee: Sony CorporationInventors: Thomas Ayers, Jinsuk Kang, Brian Carey, Noam Eshel, Fred Brady
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Publication number: 20170223291Abstract: An image sensor including a pixel circuit and an active reset circuit. The pixel circuit includes a light sensing element, a storage node selectively connected to the light sensing element, an output transistor configured to, during a readout operation, output a signal that is based on a potential of the charge storage node to an output line, and a selection transistor that controls the readout operation. The active reset circuit includes a first current path and a second current path, the first current path extending from a power supply node to the output line via the selection transistor and the output transistor, and the second current path extending from the power supply node to the output line via a first transistor and a second transistor. The active reset circuit is configured to, when the selection transistor and the first transistor are both ON, set a potential of the charge storage node based on a potential of a gate of the second transistor.Type: ApplicationFiled: February 3, 2016Publication date: August 3, 2017Inventors: Thomas Ayers, Jinsuk Kang, Brian Carey, Noam Eshel, Fred Brady
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Patent number: 8953075Abstract: An active pixel CMOS image sensor implements full frame digital correlated double sampling (CDS) with global shutter where all the pixels in the image sensor are reset at substantially the same time and all the pixels in the image sensor integrate incident light at substantially the same time and for substantially the same time duration and correlated double sampling cancellation is performed in the digital domain. In one embodiment, the image sensing device includes an array of light sensing elements, a timing and control circuit and analog-to-digital converters. The timing and control circuit is operative to reset the light sensing elements in the array and to control the array of light sensing elements to integrate incident light. The pixel reset values are cancelled from the corresponding light dependent pixel values for each of the light sensing elements to generate correlated double sampling (CDS) corrected digital output pixel values.Type: GrantFiled: March 30, 2012Date of Patent: February 10, 2015Assignee: Pixim, Inc.Inventors: Thomas Ayers, Frederick Thomas Brady, Jinsuk Kang, Ping Wah Wong
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Patent number: 8847136Abstract: An image sensor including an array of pixel elements is operated according to two operation modes to modulate the conversion gain of the pixel to operate the image sensor based on the impinging light conditions. More specifically, an image sensor pixel element is operated in a high conversion gain mode for low light conditions and in a low conversion gain mode for bright light conditions. The low conversion gain mode implements charge sharing between the floating diffusion and the photodiode. The low conversion gain mode further implements partial reset where the photodiode and the floating diffusion are reset to the same potential and to a potential slightly less than the pinning voltage of the photodiode.Type: GrantFiled: December 21, 2011Date of Patent: September 30, 2014Assignee: PIXIM, Inc.Inventors: Thomas Ayers, Frederick Thomas Brady, Jinsuk Kang, Sungin Hwang, Sen Yu
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Publication number: 20140110344Abstract: Compositions and methods for remediation of oil spills in a oil spill impacted water environment are described. The methods may further include degrading spilled oil by oxidation or bioremediation.Type: ApplicationFiled: June 9, 2011Publication date: April 24, 2014Inventors: George E. Hoag, John B. Collins, Jeffrey Thomas Ayers
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Publication number: 20130258151Abstract: An active pixel CMOS image sensor implements full frame digital correlated double sampling (CDS) with global shutter where all the pixels in the image sensor are reset at substantially the same time and all the pixels in the image sensor integrate incident light at substantially the same time and for substantially the same time duration and correlated double sampling cancellation is performed in the digital domain. In one embodiment, the image sensing device includes an array of light sensing elements, a timing and control circuit and analog-to-digital converters. The timing and control circuit is operative to reset the light sensing elements in the array and to control the array of light sensing elements to integrate incident light. The pixel reset values are cancelled from the corresponding light dependent pixel values for each of the light sensing elements to generate correlated double sampling (CDS) corrected digital output pixel values.Type: ApplicationFiled: March 30, 2012Publication date: October 3, 2013Applicant: PIXIM, INC.Inventors: Thomas Ayers, Frederick Thomas Brady, Jinsuk Kang, Ping Wah Wong
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Publication number: 20130020466Abstract: An image sensor including an array of pixel elements is operated according to two operation modes to modulate the conversion gain of the pixel to operate the image sensor based on the impinging light conditions. More specifically, an image sensor pixel element is operated in a high conversion gain mode for low light conditions and in a low conversion gain mode for bright light conditions. The low conversion gain mode implements charge sharing between the floating diffusion and the photodiode. The low conversion gain mode further implements partial reset where the photodiode and the floating diffusion are reset to the same potential and to a potential slightly less than the pinning voltage of the photodiode.Type: ApplicationFiled: December 21, 2011Publication date: January 24, 2013Applicant: PIXIM, INC.Inventors: Thomas Ayers, Frederick Thomas Brady, Jinsuk Kang, Sungin Hwang, Sen Yu
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Patent number: 7730514Abstract: A system for converting digital signals in a cable network is provided. A cable head end provides a plurality of digital signals. The plurality of digital signals are grouped into a first portion and a second portion, the first portion being in a first frequency band and the second portion being in a second frequency band. The system includes a digital channel remapping module configured to select one or more digital signals from the first portion and remap the selected one or more digital signals into a first plurality of analog signals and a digital-to-analog translator configured to convert the digital signals in the second portion to a second plurality of analog signals. The first and second plurality of analog signals are combined and delivered to at least one analog device. Some or all of the second plurality of analog signals are within the first frequency band.Type: GrantFiled: June 16, 2004Date of Patent: June 1, 2010Assignee: BroadLogic Network TechnologiesInventors: Weimin Zhang, Thomas Ayers
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Patent number: 7710965Abstract: A decoder includes a transport engine configured to receive programs and extract timing information and timestamps embedded in the programs. An adder is configured to add a set of timing offsets to the sets of timing information to adjust the timing information from a first time basis to a second time basis. Sums of the timing offsets and the timing information are referred to the mapped-timing information. A correction engine is configured to update the timing offsets as timing information is encountered in the programs, and an offset register is configured to: receive the timing offsets, store the timing offsets, and transfer the timing offsets to the adder. The adder is also configured to add the timing offsets to the timestamps to adjust the time basis of the timestamps from the first time basis to the second time basis. A program is decoder configured to receive the adjusted timestamps to decode the programs.Type: GrantFiled: November 23, 2004Date of Patent: May 4, 2010Assignee: Broadlogic Network Technologies Inc.Inventors: Binfan Liu, Thomas Ayers, Weimin Zhang
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Publication number: 20080120712Abstract: A method and system for extending the range of a security token allow a system to have a security token be utilized remotely from the system that will receive information and signals from that security token. A remote token extender can interface with a security token (such as an identity (or ID) token), configure the signals and information associated with that security token into a format for transmission across a selected media (such as a network), and transmit those signals and information across that media. At the receiving end, a local token extender can reconstitute those signals and information for use by a complementary device (such as an ID card reader) at the local system.Type: ApplicationFiled: November 20, 2007Publication date: May 22, 2008Applicant: TELOS CORPORATIONInventor: Thomas Ayers
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Publication number: 20060254008Abstract: A power washer is provided with a transport frame, a wash unit and a gun. The wash unit and the gun may be separated from the transport frame to be used in multiple modes. Possible modes include a walk-behind mode, a spray mode and hand wash modes. A quick connection is also provided to make it easier to disconnect and reconnect various components of the power washer.Type: ApplicationFiled: March 14, 2006Publication date: November 16, 2006Inventors: Klaus Hahn, Charles Long, Thomas Ayers
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Publication number: 20060136768Abstract: A decoder includes a transport engine configured to receive programs and extract timing information and timestamps embedded in the programs. An adder is configured to add a set of timing offsets to the sets of timing information to adjust the timing information from a first time basis to a second time basis. Sums of the timing offsets and the timing information are referred to the mapped-timing information. A correction engine is configured to update the timing offsets as timing information is encountered in the programs, and an offset register is configured to: receive the timing offsets, store the timing offsets, and transfer the timing offsets to the adder. The adder is also configured to add the timing offsets to the timestamps to adjust the time basis of the timestamps from the first time basis to the second time basis. A program is decoder configured to receive the adjusted timestamps to decode the programs.Type: ApplicationFiled: November 23, 2004Publication date: June 22, 2006Applicant: BroadLogic Network Technologies Inc.Inventors: Binfan Liu, Thomas Ayers, Weimin Zhang
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Patent number: 7051171Abstract: A deinterleaver for performing high-speed multi-channel forward error correction using external SDRAM is provided. According to one exemplary aspect, the deinterleaver performs both read and write accesses to the SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The data bus length of the SDRAM is designed to be twice the deinterleaving symbol size thereby allowing bandwidth to be increased. The deinterleaver accesses data in the SDRAM as read blocks and write blocks. Each block includes a predetermined number of data words to be interleaved/deinterleaved. The ACTIVE command for one block is issued when a preceding block is being processed. Data in one read/write block has the same row address within the same bank of the SDRAM.Type: GrantFiled: April 11, 2003Date of Patent: May 23, 2006Assignee: BroadLogic Network Technologies, Inc.Inventors: Binfan Liu, Zhongqiang Wang, Thomas Ayers
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Patent number: 5363952Abstract: In a materials treating furnace, a belt is provided for transporting articles to be treated through a high temperature treatment zone. The belt comprises a succession of interwoven links, each of which is made up of a length of tungsten wire which has been heated and wound around an elliptical mandrel to provide a link which is in the form of a slightly flattened helix having no sharp bends. The interweaving of the helical links provides a large number of interlocking contact points between successive links.Type: GrantFiled: September 10, 1993Date of Patent: November 15, 1994Assignee: Centorr/Vacuum Industries, Inc.Inventors: Charles W. Miller, Jr., John Currier, Larry Duclos, Thomas Ayer