Abstract: Hardware based prefetching for processor systems is implemented. A prefetch unit can be provided in a cache subsystem that allocates a prefetch tracker in response to a demand request for a cache line that missed. In response to subsequent demand requests to consecutive cachelines, a confidence indicator is increased. In response to further demand misses and a confidence indicator value, a prefetch tier is increased, which allows the prefetch tracker to initiate prefetch requests for more cachelines. Requests for cachelines that are more than two cachelines apart within a match window for the allocated prefetch tracker decreases the confidence faster than requests for consecutive cachelines increase confidence. An age counter tracks when a last demand request within the match window was received. The prefetch tier can be decreased in response to reduced confidence and increased age.

Abstract: A method and apparatus for a multiprocessor system to simultaneously process multiple data write command issued from one or more peripheral component interface (PCI) devices by controlling and limiting notification of invalidated address information issued by one memory controller managing one group of multiprocessors in a plurality of multiprocessor groups. The method and apparatus permits a multiprocessor system to almost completely process a subsequently issued write command from a PCI device or other type of computer peripheral device before a previous write command has been completely processed by the system. The disclosure is particularly applicable to multiprocessor computer systems which utilize non-uniform memory access (NUMA).

Abstract: A method is provided for allocating system resources across multiple nodes of a system communicating through a hardware device. The method provides for allocation of transaction units or identifiers in an allocating component for use in a multiple target component which may be in a distinct target node within the multiple node system. Based on the operations or requests that a target node receives from multiple external request source nodes, each requiring the use of target transaction unit objects such as transaction identification bits, the method provides inclusion of such information in the initial request to a target node which allows any data transmission between the source node and the target node, or the target node and the source node to be accomplished without any further intervention by the allocating component. Such component may be a local memory control agent or device.

Abstract: Allocating potentially needed resources for a transaction before having completely received the transaction is disclosed. An initial part of a transaction is received in first clock cycle. The resources potentially needed by the transaction are determined based on the initial part thereof that has been received, and allocated. The transaction then proceeds. The final part of the transaction is received in a final clock cycle. The resources actually needed by the transaction from the resources previously allocated are determined based on the remaining part thereof that has been received. Any unneeded remaining resources are then deallocated.

Abstract: A method and apparatus for providing cache coherence in a multiprocessor system which is configured into two or more nodes with memory local to each node and a tag and address crossbar system and a data crossbar system which interconnects all nodes. The disclosure is applicable to multiprocessor computer systems which utilize system memory distributed over more than one node and snooping of data states in each node which utilizes memory local to that node. Global snooping is used to provide a single point of serialization of data tags. A central crossbar controller examines cache state tags of a given address line for all nodes simultaneously and issues an appropriate reply back to a node requesting data while generating other data requests to any other node in the system for the purpose of maintaining cache coherence and supplying the requested data. The system utilizes memory local to each node by dividing such memory into local and remote categories which are mutually exclusive for any given cache line.

Abstract: A method and apparatus for a mutiprocessor system to simultaneously process multiple data write command issued from one or more peripheral component interface (PCI) devices by controlling and limiting notification of invalidated address information issued by one memory controller managing one group of multiprocessors in a plurality of mutiprocessor groups. The method and apparatus permits a multiprocessor system to almost completely process a subsequently issued write command from a PCI device or other type of computer peripheral device before a previous write command has been completely processed by the system. The disclosure is particularly applicable to multiprocessor computer systems which utilize non-uniform memory access (NUMA).

Abstract: A means and method to receive and store a continuous flow of data items being processed in a data processing system in which data items are received from multiple sources simultaneously. The invention provided for simultaneous retrieval of previously stored data from multiple destinations while providing low latency of the retrieved data. The invention utilizes multi-port random access memory or register arrays with fewer ports than the number of actual data sources or data destinations within the system. The disclosure teaches a means of providing the control of data flow to multi-port simultaneous access memory systems, utilizing the control paths in the memory control systems rather than the data paths in such systems. The system eliminates or reduces the need for memory buffers to manage data flow into or out of system memory devices which have a limited number of ports or paths connecting system memory to the input and output systems of the data processing system.

Abstract: A method of classification of transaction address conflicts in a computer system for ensuring efficient ordering in a two-level snoopy cache architecture. The disclosure provides a method of classification and handling of address conflicts within a system to minimize the impact that address ordering places in a multiprocessor system with multiple memory control agents generating potentially conflicting addresses. A set of classification for each potential transaction conflict is provided against which decisions are provided which identifies the earliest point at which a subsequent transaction within the system may proceed to the same address identified by a previous transaction in the system. Classification of transactions are provided in several high level classes which define how such transactions within the system are handled based on the method disclosed.

Abstract: Allocating potentially needed resources for a transaction before having completely received the transaction is disclosed. An initial part of a transaction is received in first clock cycle. The resources potentially needed by the transaction are determined based on the initial part thereof that has been received, and allocated. The transaction then proceeds. The final part of the transaction is received in a final clock cycle. The resources actually needed by the transaction from the resources previously allocated are determined based on the remaining part thereof that has been received. Any unneeded remaining resources are then deallocated.

Abstract: Assigning a building block collector agent to receive acknowledgments from other building block agents is disclosed. A memory-line request is received from a requestor agent that is one of a number of agents. Each agent has a shared memory to share among the agents, as well as a cache to temporarily store a limited number of memory lines of the shared memories of the other agents. A collector agent, which is one of the agents, is dynamically assigned for receiving acknowledgments from the agents. This dynamic assignment is based on the type of memory line-related request, and/or the global state of the caches of the agents.

Abstract: A means and method to receive and store a continuous flow of data items being processed in a data processing system in which data items are received from multiple sources simultaneously. The invention provided for simultaneous retrieval of previously stored data from multiple destinations while providing low latency of the retrieved data. The invention utilizes multi-port random access memory or register arrays with fewer ports than the number of actual data sources or data destinations within the system. The disclosure teaches a means of providing the control of data flow to multi-port simultaneous access memory systems, utilizing the control paths in the memory control systems rather than the data paths in such systems. The system eliminates or reduces the need for memory buffers to manage data flow into or out of system memory devices which have a limited number of ports or paths connecting system memory to the input and output systems of the data processing system.

Abstract: A method and apparatus for a mutiprocessor system to simultaneously process multiple data write command issued from one or more peripheral component interface (PCD devices by controlling and limiting notification of invalidated address information issued by one memory controller managing one group of multiprocessors in a plurality of mutiprocessor groups. The method and apparatus permits a multiprocessor system to almost completely process a subsequently issued write command from a PCI device or other type of computer peripheral device before a previous write command has been completely processed by the system. The disclosure is particularly applicable to multiprocessor computer systems which utilize non-uniform memory access (NUMA).

Abstract: A method and apparatus for providing cache coherence in a multiprocessor system which is configured into two or more nodes with memory local to each node and a tag and address crossbar system and a data crossbar system which interconnects all nodes. The disclosure is applicable to multiprocessor computer systems which utilize system memory distributed over more than one node and snooping of data states in each node which utilizes memory local to that node. Global snooping is used to provide a single point of serialization of data tags. A central crossbar controller examines cache state tags of a given address line for all nodes simultaneously and issues an appropriate reply back to a node requesting data while generating other data requests to any other node in the system for the purpose of maintaining cache coherence and supplying the requested data. The system utilizes memory local to each node by dividing such memory into local and remote categories which are mutually exclusive for any given cache line.

Abstract: A method of allocating hardware resources in a multiprocessor computer system which utilizes non-uniform memory access and distributed system resources across multiple nodes. The disclosure provides a method for allocating system resources across multiple nodes of a system communicating through a hardware device comprised of a tag and address crossbar system interconnecting node control devices. The method provides for allocation of transaction units or transaction identifiers in an allocating component for use in a multiple target component which may be in a distinct target node within the multiple node system.

Abstract: A method of classification of transaction address conflicts in a computer system for ensuring efficient ordering in a two-level snoopy cache architecture. The disclosure provides a method of classification and handling of address conflicts within a system to minimize the impact that address ordering places in a multiprocessor system with multiple memory control agents generating potentially conflicting addresses. A set of classification for each potential transaction conflict is provided against which decisions are provided which identifies the earliest point at which a subsequent trasaction within the system may proceed to the same address identified by a previous transaction in the system. Classification of transactions are provided in several high level classes which define how such transactions within the system are handled based on the method disclosed.

Abstract: A multinode multiprocessor computer system with distributed local clocks wherein a local clock may be synchronized with other clocks in the system without affecting the operation of the other clocks. A local clock to be synchronized is reset and counts an elapsed time since the reset. Simultaneously with resetting the local clock, a clock value from a clock on a source node is stored. The clock value from the source node is copied to the node to be synchronized and added to the elapsed time. The resulting summation is then stored in the local clock to be synchronized. As a result, the local clock is synchronized to the clock on the source node. In one system embodiment, the local clock includes a dynamic register and a base register and an adder adds the two portions together to generate an output of the local clock. For a node being synchronized, the dynamic portion is reset and allowed to count the elapsed time while the base portion is loaded with a clock value copied from the source node.

Abstract: In a digital computer with a cache comprised of N sets labeled 0 to N-1, cache tag memory for each set is divided into primary and mirror parts, each part with sufficient capacity to store a number of cache tags equal to the number of cache blocks storable in a cache memory associated with each set. Every modification or installation of cache tags in the primary part of a set x is accompanied or followed by identical modification or installation of cache tags in the mirror part of a set F(x), where F is a one-to-one function that maps the set of integers from 0 to N-1 onto itself. Cache tag lookup retrieves a first set of N cache tags from the primary part of each cache tag memory, and parity checking is performed on each tag. If a parity error is found, a set of cache tags is retrieved from the mirror part of the cache tag memories, and parity checking is again performed. If no error is found, cache processing proceeds normally.

Abstract: An information processing system comprises a high speed noninterlocked system bus 12 which couples together a plurality of system units including a main memory and a system bus interface (SBI) unit 34. The system bus interface unit is further coupled to an I/O bus 42 having a plurality of I/O Processors 44, 46 coupled thereto. The system bus interface includes read and write buffer storage for buffering information units being transferred between the system bus and the I/O bus. The I/O bus includes two signal lines which differentiate the condition of an I/O bus SBI BUSY signal line. One of these two signal lines indicates when the SBI read buffer is full while the other signal line indicates when the SBI write buffer is full. The SBI Busy signal line indicates when either of these conditions exist. I/O processors are enabled to differentiate between read and write buffer full conditions, thereby effectively increasing the bandwidth of the I/O bus.

Abstract: An information processing system comprises a high speed noninterlocked system bus 12 which couples together a plurality of system units including a main memory and a system bus interface (SBI) unit 34. The system bus interface unit is further coupled to an I/O bus 42 having a plurallity of I/O Processors 44, 46 coupled thereto. The system bus interface includes read and write buffer storage for buffering information units being transferred between the system bus and the I/O bus. The I/O bus includes two signal lines which differentiate the condition of an I/O bus SBI BUSY signal line. One of these two signal lines indicates when the SBI read buffer is full while the other signal line indicates when the SBI write buffer is full. The SBI Busy signal line indicates when either of these conditions exist. I/O processors are enabled to differentiate between read and write buffer full conditions, thereby effectively increasing the bandwidth of the I/O bus.