Abstract: A method and structure for improving a content addressable memory array has a plurality of serially connected memory sub-arrays (which include at least one memory cell), a matchline connected to each of the sub-arrays, a valid memory cell, a comparator receiving input from the matchline and valid memory cell, a sinkline output from the comparator, and a precharge device. The sinkline and matchline are reset from a first voltage to a second voltage depending upon the results of a compare operation of the input data to the data in the storage device. When the second voltage appears on the matchline and the first voltage appears on the sinkline this indicates a match between the data within all of the sub-arrays and the input data.

Abstract: A method and structure for improving a content addressable memory array has a plurality of serially connected memory sub-arrays (which include at least one memory cell), a matchline connected to each of the sub-arrays, a valid memory cell, a comparator receiving input from the matchline and valid memory cell, a sinkline output from the comparator, and a precharge device. The sinkline and matchline are reset from a first voltage to a second voltage depending upon the results of a compare operation of the input data to the data in the storage device. When the second voltage appears on the matchline and the first voltage appears on the sinkline this indicates a match between the data within all of the sub-arrays and the input data. If the second voltage appears on the sinkline this indicates a mismatch between data within any of the sub-arrays and the input data, or an invalid status within the valid memory cell and maintains the sinkline at the second voltage.

Abstract: A method and structure for content addressable memory structure having a memory array of words, each word having multiple memory bits and a plurality of matchlines. Each of the matchlines is connected to one of the words and a matchline compare circuit is connected to the matchlines and is adapted to test all of the words individually. The matchline compare circuit includes a plurality of comparators equal in number to a number of the words, such that each word is connected to a dedicated comparator to allow each word in the memory array to be individually tested.

Abstract: A content addressable memory device comprises a NAND-NOR chain comprised an alternating sequence of NAND and NOR stages; the NAND stages, each including a first CAM cell comprising a first memory cell that stores a first data bit and a first compare cell that compares the first data bit with a first compare bit and generates a first compare signal indicating whether the first data bit matches the first compare bit and a logical NAND gate that combines the first compare signals of other first CAM cells in the NAND stage; the NOR stages, each including a second CAM cell comprising a second memory cell that stores a second data bit and a second compare cell that compares the second data bit with a second compare bit and generates a second compare signal indicating whether the second data bit matches the second compare bit and a logical NOR gate that combines the second compare signals of other second CAM cells in the NOR stage; and the NAND-NOR chain generating a match signal indicating a match of all the compar