Patents by Inventor Thomas B. Maciukenas

Thomas B. Maciukenas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for efficiently managing architectural register state of a processor
    Patent number: 9804842
    Abstract: An apparatus and method for efficiently managing the architectural state of a processor.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: October 31, 2017
    Assignee: INTEL CORPORATION
    Inventors: Jesus Corbal San Adrian, Dennis R. Bradford, Benjamin C. Chaffin, Taraneh Bahrami, Jonathan C. Hall, Thomas B. Maciukenas, Roger Gramunt, Rohan Sharma
  • METHOD AND APPARATUS FOR EFFICIENTLY MANAGING ARCHITECTURAL REGISTER STATE OF A PROCESSOR
    Publication number: 20160179527
    Abstract: An apparatus and method for efficiently managing the architectural state of a processor.
    Type: Application
    Filed: December 23, 2014
    Publication date: June 23, 2016
    Inventors: Jesus Corbal, Dennis R. Bradford, Benjamin C. Chaffin, Taraneh Bahrami, Jonathan C. Hall, Thomas B. Maciukenas, Roger Gramunt, Rohan Sharma
  • Byte swap operation for a 64 bit operand
    Patent number: 7047383
    Abstract: A method for a byte swap operation on a 64 bit operand. The method of one embodiment comprises accessing an operand stored in a register. The operand is comprised of a plurality of bytes of data. A first set of bytes located in an upper half of said register is reordered. A second set of bytes located in a lower half of said register is reordered. The first set of bytes is swapped with the second set of bytes, wherein the first set of bytes is relocated to the lower half of the register and the second set of bytes is relocated to the upper half of the register.
    Type: Grant
    Filed: July 11, 2002
    Date of Patent: May 16, 2006
    Assignee: Intel Corporation
    Inventor: Thomas B. Maciukenas
  • Byte swap operation for a 64 bit operand
    Publication number: 20040010676
    Abstract: A method for a byte swap operation on a 64 bit operand. The method of one embodiment comprises accessing an operand stored in a register. The operand is comprised of a plurality of bytes of data. A first set of bytes located in an upper half of said register is reordered. A second set of bytes located in a lower half of said register is reordered. The first set of bytes is swapped with the second set of bytes, wherein the first set of bytes is relocated to the lower half of the register and the second set of bytes is relocated to the upper half of the register.
    Type: Application
    Filed: July 11, 2002
    Publication date: January 15, 2004
    Inventor: Thomas B. Maciukenas