Abstract: Techniques are disclosed relating to power management in a processing circuit that includes a set of functional blocks and performance counter registers configured to store utilization values indicative of utilization of associated ones of the set of functional blocks. A register interface circuit is configured to periodically sample the processing circuit to obtain aggregated utilization values generated from utilization values stored in the performance counter registers and write the aggregated utilization values to the set of trace buffer. A power management processor is configured to utilize a set of information stored in the set of trace buffers to determine whether to change a performance state of the processing circuit, the set of information including time-domain and frequency-domain representations of utilization of the processing circuit. In other embodiments, a functional block that is a hardware limiter of the processing circuit may be determined.

Abstract: A method and apparatus for clipping an object element include processing that begins by ascribing barycentric coordinates to each original vertices of an object-element wherein each barycentric coordinate is a weighting factor with respect to a corresponding original vertex. The processing continues by obtaining clipping distances for each original vertex with respect to a clipping plane. For a new vertex of an object-element that represents an intersection of an edge of the object-element with the clipping plane, the process continues by determining a barycentric coordinate for the new vertex. The determination of the new vertex is based on the barycentric coordinates of the original vertices defining the edge and the clipping distances. Having determined the barycentric coordinates for the new vertices corresponding to a clipping plane, the process is repeated for each of a plurality of other clipping planes that intersect the object-element.