Patents by Inventor Thomas Böttner

Thomas Böttner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit arrangement with NPN and PNP bipolar transistors and corresponding production method
    Patent number: 7968416
    Abstract: An integrated circuit arrangement and fabrication method is provided. The integrated circuit arrangement contains an NPN transistor and a PNP transistor. The PNP transistor contains an emitter connection region and a cutout. The cutout delimits the width of the emitter connection region. The electrically conductive material of the connection region laterally overlaps the cutout.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: June 28, 2011
    Assignee: Infineon Technologies AG
    Inventors: Thomas Böttner, Stefan Drexl, Thomas Huttner, Martin Seck
  • Integrated circuit arrangement with NPN and PNP bipolar transistors and corresponding production method
    Patent number: 7592648
    Abstract: An integrated circuit arrangement and fabrication method is provided. The integrated circuit arrangement contains an NPN transistor and a PNP transistor. The PNP transistor contains an emitter connection region and a cutout. The cutout delimits the width of the emitter connection region. The electrically conductive material of the connection region laterally overlaps the cutout.
    Type: Grant
    Filed: December 6, 2005
    Date of Patent: September 22, 2009
    Assignee: Infineon Technologies AG
    Inventors: Thomas Böttner, Stefan Drexl, Thomas Huttner, Martin Seck
  • Integrated circuit arrangement having PNP and NPN bipolar transistors, and fabrication method
    Patent number: 7038255
    Abstract: An explanation is given of, inter alia, an integrated circuit arrangement (100) containing an npn transistor (102) and a pnp transistor (104). Transistors with outstanding electrical properties are produced if the pnp transistor contains a cutout (142) for an edge terminal region (120) and if the edge terminal region (120) has a part near the substrate which is arranged in the cutout (142) and a part remote from the substrate which is arranged outside the cutout (142) and overlaps the base terminal region (139).
    Type: Grant
    Filed: June 21, 2004
    Date of Patent: May 2, 2006
    Assignee: Infineon Technologies AG
    Inventors: Thomas Böttner, Stefan Drexl, Thomas Huttner, Martin Seck