Abstract: A packet processor implemented in hardware. The packet processor includes a processing pipeline including a plurality of processing elements. The plurality of processing elements are configured to process a first data packet transferred sequentially through the plurality of processing elements. The first data packet includes information indicating a period of time that at least a first processing element of the plurality of processing elements uses to process the first data packet. The first processing element is prevented from processing other data packets due to performing processing on the first data packet during the period of time. A packet rate shaper is configured to, prior to the first data packet entering the processing pipeline, read the information in the first data packet, selectively increment and decrement a token value, and selectively grant the first data packet access to the processing pipeline based on the information and based on the token value.