Abstract: A method and apparatus is disclosed for minimizing power virus in a network on chip. The method includes an operational metric related to a node with at least one threshold, the node configured to manage communication of a first number of outbound transactions; determining, based on the comparison, a second number of outbound transactions from the first number of outbound transactions that are allowed from the node; and communicating the second number of outbound transactions. An apparatus for minimizing power virus in a network on chip is also disclosed.

Abstract: Aspects of the present disclosure propose techniques for testing a network on chip (NoC). An exemplary method may generally include generating, at a source node of the NoC, a first plurality of packets according to a first pre-defined pattern of a plurality of pre-defined patterns, wherein each pre-defined pattern is designed to provoke transients in the NoC, generating, at the source node of the NoC, a second plurality of packets according to the first pre-defined pattern of the plurality of pre-defined patterns, generating the transients in the NoC by transmitting the first plurality of packets and thereafter transmitting the second plurality of packets, and verifying at least one of the first plurality of packets or the second plurality of packets are successfully received at a destination node of the NoC despite the generated transients.

Abstract: Selective insertion of a deadlock recovery buffer in a bus interconnect for deadlock recovery is provided. A bus interconnect is provided that includes router nodes configured to receive new bus transaction messages from agent devices. The router nodes route the received bus transaction messages to other destination router nodes in the bus interconnect to be communicated to designated agent devices. To recover from a deadlock condition when buffers of all router nodes are full, thus halting forward progress of bus transaction messages, a deadlock recovery circuit is provided. The deadlock recovery circuit is configured to detect a bus deadlock condition in the bus interconnect. In response, the deadlock recovery circuit is configured to insert a deadlock recovery buffer that has additional buffer entries in the bus interconnect as another router node to allow forward progress of bus transaction messages to continue to recover from the deadlock condition.

Abstract: Systems and methods for of deadlock-free routing in a partial two-dimensional (2D) mesh network include at least one restricted path in a turn model for deadlock-free routing of a data packet from a first node to a second node of the partial mesh network. The at least one restricted path is enabled with a terminating channel ending in the second node and used for routing the data packet through the terminating channel. The terminating channel may include a physical terminating channel or a virtual terminating channel.