Abstract: A frequency linearity measurement circuit configured to measure a frequency linearity of a frequency signal includes: a first measurement circuit having a counter, where the counter is controlled by a gate signal having a gate signal period, where the first measurement circuit is configured to generate a first estimate of an integer number of clock cycles of the frequency signal within a respective gate signal period of the gate signal; a second measurement circuit having a time-to-digital converter (TDC), where the TDC is controlled by the gate signal, and is configured to generate a second estimate of a fractional number of clock cycle of the frequency signal within the respective gate signal period of the gate signal; and a reference measurement circuit configured to generate a third estimate of an expected number of clock cycles within the respective gate signal period of the gate signal.

Abstract: A frequency linearity measurement circuit configured to measure a frequency linearity of a frequency signal includes: a first measurement circuit configured to generate a first estimate of an integer number of clock cycles of the frequency signal within a respective gate signal period of a gate signal; a second measurement circuit comprising a time-to-digital converter (TDC) configured to generate a second estimate of a fractional number of clock cycle of the frequency signal within the respective gate signal period; a reference measurement circuit configured to generate a third estimate of an expected number of clock cycles within the respective gate signal period; and a closed-loop frequency tracking circuit configured to track a frequency error between an expected frequency and a measured frequency, where the expected frequency and the measured frequency are determined based on the third estimate and on a sum of the first estimate and the second estimate, respectively.

Abstract: A digital phase-locked loop (DPLL) circuit includes: a first time-to-digital converter (TDC) and a first digital loop filter (DLF) that are configured to be coupled between a reference clock source and a digitally controlled oscillator (DCO), where the first TDC is configured to, during an acquisition mode, generate a phase error by: receiving a reference clock signal from the reference clock source; receiving a clock signal that is based on an output of the DCO divided by a dividing factor, computing a phase error using the reference clock signal and the clock signal; detecting cycle slipping in the computed phase error; and in response to detecting the cycle slipping, modifying the computed phase error to reduce the impact of cycle slipping on the DPLL circuit; and a first frequency divider circuit configured to generate the clock signal by dividing the output of the DCO by the dividing factor.

Abstract: A method of operating a pipelined analog-to-digital converter (ADC) having a plurality of output stages includes: performing a first calibration process for the pipelined ADC to update a parameter vector of the pipelined ADC, where components of the parameter vector are used for correcting nonlinearity of the pipelined ADC, where performing the first calibration process includes: providing an input signal to the pipelined ADC; converting, by the pipelined ADC, the input signal into a first digital output; providing a scaled version of the input signal to the pipelined ADC, where the scaled version of the input signal is generated by scaling the input signal by a scale factor; converting, by the pipelined ADC, the scaled version of the input signal into a second digital output; and calibrating the pipelined ADC using the first digital output and the second digital output.

Abstract: A method of operating a pipelined analog-to-digital converter (ADC) having a plurality of output stages includes: performing a first calibration process for the pipelined ADC to update a parameter vector of the pipelined ADC, where components of the parameter vector are used for correcting nonlinearity of the pipelined ADC, where performing the first calibration process includes: providing an input signal to the pipelined ADC; converting, by the pipelined ADC, the input signal into a first digital output; providing a scaled version of the input signal to the pipelined ADC, where the scaled version of the input signal is generated by scaling the input signal by a scale factor; converting, by the pipelined ADC, the scaled version of the input signal into a second digital output; and calibrating the pipelined ADC using the first digital output and the second digital output.

Abstract: An apparatus for shifting a digital signal having a first sample rate by a shift time to provide a shifted signal having a second sample rate is provided. The apparatus includes a sample rate converter configured to provide a value of an interpolated signal at a compensated sample time as a sample of the shifted signal, the interpolated signal being based on the digital signal. The sample rate converter is configured to modify a time interval between a sample time of the digital signal and the compensated sample time based on the shift time.

Abstract: An apparatus for shifting a digital signal having a first sample rate by a shift time to provide a shifted signal having a second sample rate is provided. The apparatus includes a sample rate converter configured to provide a value of an interpolated signal at a compensated sample time as a sample of the shifted signal, the interpolated signal being based on the digital signal. The sample rate converter is configured to modify a time interval between a sample time of the digital signal and the compensated sample time based on the shift time.

Abstract: A transmitter for generating an analog radio frequency transmit signal is provided. The transmitter includes a digital-to-analog converter configured to receive an oscillation signal and a first digital data signal to generate an analog radio frequency transmit signal. Further, the transmitter includes an oscillation signal generator configured to generate the oscillation signal with an oscillation frequency based on a second digital data signal. The transmitter additionally includes a controller configured to change a first sample frequency of the first digital data signal from a first frequency to a value different than the oscillation frequency, wherein the first frequency is at least the oscillation frequency.

Abstract: An apparatus for shifting a digital signal having a first sample rate by a shift time to provide a shifted signal having a second sample rate is provided. The apparatus includes a sample rate converter configured to provide a value of an interpolated signal at a compensated sample time as a sample of the shifted signal, the interpolated signal being based on the digital signal. The sample rate converter is configured to modify a time interval between a sample time of the digital signal and the compensated sample time based on the shift time.

Abstract: A transmitter for generating an analog radio frequency transmit signal is provided. The transmitter includes a digital-to-analog converter configured to receive an oscillation signal and a first digital data signal to generate an analog radio frequency transmit signal. Further, the transmitter includes an oscillation signal generator configured to generate the oscillation signal with an oscillation frequency based on a second digital data signal. The transmitter additionally includes a controller configured to change a first sample frequency of the first digital data signal from a first frequency to a value different than the oscillation frequency, wherein the first frequency is at least the oscillation frequency.

Abstract: An apparatus for shifting a digital signal having a first sample rate by a shift time to provide a shifted signal having a second sample rate is provided. The apparatus includes a sample rate converter configured to provide a value of an interpolated signal at a compensated sample time as a sample of the shifted signal, the interpolated signal being based on the digital signal. The sample rate converter is configured to modify a time interval between a sample time of the digital signal and the compensated sample time based on the shift time.

Abstract: One embodiment of the present invention relates to a modulation system having a phase locked loop and an adaptive control. The phased lock loop is configured to receive an input signal and an adaptive signal. The input signal is an unmodulated signal, such as a phase component or phase signal. The phase locked loop is also configured to provide an error signal and an output signal. The error signal indicates one or more modulation errors. The output signal is a modulated version of the input signal that has been corrected using the adaptive signal to mitigate the one or more modulation errors.

Abstract: One embodiment of the present invention relates to a modulation system having a phase locked loop and an adaptive control. The phased lock loop is configured to receive an input signal and an adaptive signal. The input signal is an unmodulated signal, such as a phase component or phase signal. The phase locked loop is also configured to provide an error signal and an output signal. The error signal indicates one or more modulation errors. The output signal is a modulated version of the input signal that has been corrected using the adaptive signal to mitigate the one or more modulation errors.

Abstract: An apparatus for synchronizing a data handover between a first clock domain and a second clock domain includes a calculator, a first-in-first-out storage, a synchronization pulse generator, a fill level information provider and a feedback path. The calculator is configured to provide a synchronization pulse cycle duration information describing a temporal position of synchronization pulses at a clock of the second clock domain. The first-in-first-out storage receives an input data value in synchronization with the first clock domain and provides an output data value in synchronization with the second clock domain in response to a current synchronization pulse. The fill level information provider provides fill level information describing a fill level of the FIFO. The feedback path feeds back the fill level information to the calculator to adjust the synchronization pulse cycle duration information.

Abstract: An apparatus for synchronizing a data handover is disclosed. The calculator is clocked with a clock of a first clock domain and configured to provide synchronization pulse cycle duration information describing a temporal position of a synchronization pulse at a clock of the second clock domain. The synchronization pulse generator is clocked with the clock of the second clock domain and configured to generate the synchronization pulse such that the synchronization pulse is located at the temporal position described by the synchronization pulse cycle duration information. The phase information provider is clocked with the clock of the second clock domain and configured to provide a phase information describing a phase relation between the synchronization pulse and the clock of the first clock domain. The feedback path is configured for feeding back the phase information to the calculator and to adjust the synchronization pulse cycle duration information based on the phase information.

Abstract: One embodiment of the present invention relates to a modulation system having a phase locked loop and an adaptive control. The phased lock loop is configured to receive an input signal and an adaptive signal. The input signal is an unmodulated signal, such as a phase component or phase signal. The phase locked loop is also configured to provide an error signal and an output signal. The error signal indicates one or more modulation errors. The output signal is a modulated version of the input signal that has been corrected using the adaptive signal to mitigate the one or more modulation errors.

Abstract: Embodiments of the present invention provide an apparatus for synchronizing a data handover between a first clock domain and a second clock domain. The apparatus includes a calculator, a synchronization pulse generator, a phase information provider and a feedback path. The calculator is clocked with a clock of the first clock domain and configured to provide synchronization pulse cycle duration information describing a temporal position of a synchronization pulse at a clock of the second clock domain. The synchronization pulse generator is clocked with the clock of the second clock domain and configured to generate the synchronization pulse such that the synchronization pulse is located at the temporal position described by the synchronization pulse cycle duration information. The phase information provider is clocked with the clock of the second clock domain and configured to provide a phase information describing a phase relation between the synchronization pulse and the clock of the first clock domain.

Abstract: Embodiments of the present invention provide an apparatus for synchronizing a data handover between a first clock domain and a second clock domain. The apparatus includes a calculator, a first-in-first-out storage, a synchronization pulse generator, a fill level information provider and a feedback path. The calculator is clocked with the clock of the first clock domain and configured to provide a synchronization pulse cycle duration information describing a temporal position of synchronization pulses at a clock of the second clock domain. The first-in-first-out storage is configured to take over an input data value in synchronization with the first clock domain and to provide an output data value in synchronization with the second clock domain and in response to a current synchronization pulse.

Abstract: A device may include an oscillator circuit, a control circuit, a frequency detector circuit, and a processor circuit. The oscillator circuit may include a frequency control input to output an oscillator signal. The frequency of the oscillator signal depends on an input signal applied to the frequency control input. The control circuit is configured to apply a first input signal value, a second input signal value, and a third input signal value to the frequency control input. The frequency detector circuit is configured to detect the first frequency value of the oscillator signal when the first input signal value is applied to the frequency control input, a second frequency value of the oscillator signal when the second input signal value is applied to the frequency control input, and a third frequency value of the oscillator signal when the third input signal value is applied to the frequency control input.

Abstract: A phase locked loop has a controlled oscillator for outputting an oscillator signal depending on a control signal. A comparator generates a comparison result from a comparison between a reference frequency signal and a feedback signal derived from the oscillator signal. The phase locked loop also has a filter block for filtering the comparison result and for deriving the control signal from the comparison result, where the filter block has a loop filter and a rejection filter for the frequency-selective attenuation of at least one first interference frequency in the comparison result.