Abstract: A memory device (100) comprising an array of memory cells (102.1-102.4) each comprising M memory elements (106) and a switch (104), the memory cells being addressed by word lines (108), source lines (112) and bit lines (110), wherein: a first conduction electrode of each switch is coupled to a first electrode of each of the memory elements of a single one of the memory cells; each word line is coupled to a control electrode of each switch of a single and same column of memory cells; each source line is coupled to a second conduction electrode of each switch of a single and same row of memory cells; each bit line is coupled to a second electrode of one of the memory elements of each memory cell of a single and same column of memory cells.