Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.

Abstract: A semiconductor device includes a capacitance, the numerical value of which is relevant for a device function. The capacitance is formed from a parallel connection of at least a first and a second capacitor element, wherein the first and second capacitor elements are formed in respective manufacturing steps that exhibit uncorrelated process fluctuations.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.

Abstract: A semiconductor device includes a capacitance, the numerical value of which is relevant for a device function. The capacitance is formed from a parallel connection of at least a first and a second capacitor element, wherein the first and second capacitor elements are formed in respective manufacturing steps that exhibit uncorrelated process fluctuations.

Abstract: A semiconductor component has an insulating layer which is formed on a semiconductor substrate and in which a capacitance structure (K) is formed. The capacitance structure (K) has at least two metallization planes (1 to 7) which are arranged parallel to one another and are each connected to an electrical connecting line. Arranged between the metallization planes (1 to 7) is at least one electrically conductive region (1a to 1j; 2a to 2j; 31a to 36a; 41a to 46a; 5a to 5f) for producing a capacitance surface, the electrically conductive region (1a to 1j; 2a to 2j; 31a to 36a; 41a to 46a; 5a to 5f) being electrically connected only to one of the metallization planes (1 to 7).

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.

Abstract: Two inductors formed in multiple layers of conductive layers of integrated circuits are disclosed. Symmetric portions of a first inductor and a second inductor are formed in two or more conductive layers. Portions of the first inductor in adjacent conductive layers are connected by vias, and portions of the second inductor in adjacent conductive layers are connected by vias. The first and second inductor portions form a substantially loop-shaped structure in each conductive layer. The first and second inductor vias may be positioned at the same position within the substantially loop-shaped inductor structure by alternating inner and outer radiuses, or the vias for the second inductor may be positioned opposite the vias for the first inductor within the substantially loop-shaped inductor structure, using notches in the first and second inductor portions.

Abstract: A semiconductor component includes an integrated capacitor structure embodied at least partly in an electrically conductive plane and which is patterned such that a multiplicity of strip elements are present. A first group of strip elements constitutes a first electrode of the capacitor structure and a second group of strip elements constitutes a second electrode of the capacitor structure. The first strip elements together with the second strip elements being at least partly interlinked in one another, and at least one strip element may have a non-constant width along its length.

Abstract: A semiconductor device includes a capacitance, the numerical value of which is relevant for a device function. The capacitance is formed from a parallel connection of at least a first and a second capacitor element, wherein the first and second capacitor elements are formed in respective manufacturing steps that exhibit uncorrelated process fluctuations.

Abstract: Integrated circuit arrangement having first and second signal input pads, to which a differential input signal is applied, and first and second signal outputs, at which a differential output signal is provided. The first signal output is coupled to the first signal input pad and the second signal output is coupled to the second signal input pad. A first capacitance is between the first and second signal input pads. First and second inductances are connected in series, are between the first and second signal input pads, and are connected in parallel with the first capacitance. A first terminal is at a first supply potential and a second terminal is at a second supply potential. A first electrostatic discharge element is between the first and second terminals. A second electrostatic discharge element is between the first terminal, on the one hand, and the first and second inductances, on the other hand.

Abstract: A semiconductor component includes an integrated capacitor structure embodied at least partly in an electrically conductive plane and which is patterned such that a multiplicity of strip elements are present. A first group of strip elements constitutes a first electrode of the capacitor structure and a second group of strip elements constitutes a second electrode of the capacitor structure. The first strip elements together with the second strip elements being at least partly interlinked in one another, and at least one strip element may have a non-constant width along its length.

Abstract: Two inductors formed in multiple layers of conductive layers of integrated circuits are disclosed. Symmetric portions of a first inductor and a second inductor are formed in two or more conductive layers. Portions of the first inductor in adjacent conductive layers are connected by vias, and portions of the second inductor in adjacent conductive layers are connected by vias. The first and second inductor portions form a substantially loop-shaped structure in each conductive layer. The first and second inductor vias may be positioned at the same position within the substantially loop-shaped inductor structure by alternating inner and outer radiuses, or the vias for the second inductor may be positioned opposite the vias for the first inductor within the substantially loop-shaped inductor structure, using notches in the first and second inductor portions.

Abstract: Integrated circuit arrangement having first and second signal input pads, to which a differential input signal is applied, and first and second signal outputs, at which a differential output signal is provided. The first signal output is coupled to the first signal input pad and the second signal output is coupled to the second signal input pad. A first capacitance is between the first and second signal input pads. First and second inductances are connected in series, are between the first and second signal input pads, and are connected in parallel with the first capacitance. A first terminal is at a first supply potential and a second terminal is at a second supply potential. A first electrostatic discharge element is between the first and second terminals. A second electrostatic discharge element is between the first terminal, on the one hand, and the first and second inductances, on the other hand.

Abstract: A semiconductor component has an insulating layer which is formed on a semiconductor substrate and in which a capacitance structure (K) is formed. The capacitance structure (K) has at least two metallization planes (1 to 7) which are arranged parallel to one another and are each connected to an electrical connecting line. Arranged between the metallization planes (1 to 7) is at least one electrically conductive region (1a to 1j; 2a to 2j; 31a to 36a; 41a to 46a; 5a to 5f) for producing a capacitance surface, the electrically conductive region (1a to 1j; 2a to 2j; 31a to 36a; 41a to 46a; 5a to 5f) being electrically connected only to one of the metallization planes (1 to 7).