Patents by Inventor Thomas Benjamin Berg
Thomas Benjamin Berg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9141545Abstract: A cache coherence manager, disposed in a multi-core microprocessor, includes a request unit, an intervention unit, a response unit and an interface unit. The request unit receives coherent requests and selectively issues speculative requests in response. The interface unit selectively forwards the speculative requests to a memory. The interface unit includes at least three tables. Each entry in the first table represents an index to the second table. Each entry in the second table represents an index to the third table. The entry in the first table is allocated when a response to an associated intervention message is stored in the first table but before the speculative request is received by the interface unit. The entry in the second table is allocated when the speculative request is stored in the interface unit. The entry in the third table is allocated when the speculative request is issued to the memory.Type: GrantFiled: December 2, 2014Date of Patent: September 22, 2015Assignee: ARM Finance Overseas LimitedInventors: William Lee, Thomas Benjamin Berg
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Publication number: 20150089157Abstract: A cache coherence manager, disposed in a multi-core microprocessor, includes a request unit, an intervention unit, a response unit and an interface unit. The request unit receives coherent requests and selectively issues speculative requests in response. The interface unit selectively forwards the speculative requests to a memory. The interface unit includes at least three tables. Each entry in the first table represents an index to the second table. Each entry in the second table represents an index to the third table. The entry in the first table is allocated when a response to an associated intervention message is stored in the first table but before the speculative request is received by the interface unit. The entry in the second table is allocated when the speculative request is stored in the interface unit. The entry in the third table is allocated when the speculative request is issued to the memory.Type: ApplicationFiled: December 2, 2014Publication date: March 26, 2015Inventors: William Lee, Thomas Benjamin Berg
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Patent number: 8930634Abstract: A cache coherence manager, disposed in a multi-core microprocessor, includes a request unit, an intervention unit, a response unit and an interface unit. The request unit receives coherent requests and selectively issues speculative requests in response. The interface unit selectively forwards the speculative requests to a memory. The interface unit includes at least three tables. Each entry in the first table represents an index to the second table. Each entry in the second table represents an index to the third table. The entry in the first table is allocated when a response to an associated intervention message is stored in the first table but before the speculative request is received by the interface unit. The entry in the second table is allocated when the speculative request is stored in the interface unit. The entry in the third table is allocated when the speculative request is issued to the memory.Type: GrantFiled: February 13, 2014Date of Patent: January 6, 2015Assignee: ARM Finance Overseas LimitedInventors: William Lee, Thomas Benjamin Berg
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Publication number: 20140164714Abstract: A cache coherence manager, disposed in a multi-core microprocessor, includes a request unit, an intervention unit, a response unit and an interface unit. The request unit receives coherent requests and selectively issues speculative requests in response. The interface unit selectively forwards the speculative requests to a memory. The interface unit includes at least three tables. Each entry in the first table represents an index to the second table. Each entry in the second table represents an index to the third table. The entry in the first table is allocated when a response to an associated intervention message is stored in the first table but before the speculative request is received by the interface unit. The entry in the second table is allocated when the speculative request is stored in the interface unit. The entry in the third table is allocated when the speculative request is issued to the memory.Type: ApplicationFiled: February 13, 2014Publication date: June 12, 2014Inventors: William Lee, Thomas Benjamin Berg
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Publication number: 20130067284Abstract: A method of coordinating trace information in a multiprocessor system includes receiving processor trace information from a set of processors. The processor trace information from each processor includes a processor identity and a coherence indicator that demarks selective shared memory transactions. Coherence manager trace information is generated for each of the processors. The coherence manager trace information for each processor includes trace metrics and a coherence indicator.Type: ApplicationFiled: September 10, 2012Publication date: March 14, 2013Applicant: MIPS TECHNOLOGIES, INC.Inventors: Thomas Benjamin Berg, Ryan C. Kinter, Jaidev Prasad Patwardhan, Radhika Thekkath
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Publication number: 20120290780Abstract: A method of fetching data from a cache begins by preparing to fetch a first set of cache ways for a first data word of a first cache line a using a first thread. Next, in parallel, a second set cache ways for a first data word of a second cache line is prepared to be fetched using a second thread, and data associated with each cache way of the first set of cache ways are fetched using the first thread. Also performed in parallel, data associated with each cache way of the second set of cache ways is fetched using the second thread and a third set of cache ways for a second data word of the first cache line is prepared to be fetched using the first thread based on a selected cache way, the selected cache way selected from the first set of cache ways.Type: ApplicationFiled: January 27, 2012Publication date: November 15, 2012Applicant: MIPS Technologies Inc.Inventors: Ryan C. Kinter, Thomas Benjamin Berg, Matthias Knoth
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Patent number: 8230202Abstract: A computer readable storage medium includes executable instructions to characterize a coherency controller. The executable instructions define ports to receive processor trace information from a set of processors. The processor trace information from each processor includes a processor identity and a condensed coherence indicator. Circuitry produces a trace stream with trace metrics and condensed coherence indicators.Type: GrantFiled: March 31, 2008Date of Patent: July 24, 2012Assignee: MIPS Technologies, Inc.Inventors: Thomas Benjamin Berg, Ryan C. Kinter, Jaidev Prasad Patwardhan, Radhika Thekkath
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Patent number: 8001283Abstract: A system, apparatus and method for managing input/output requests in a multi-processor system is disclosed. An IO coherence unit includes an IO request handler, a variable size transaction table, and an IO response handler. The size of the transaction table varies according to the number of pending IO requests. The IO request handler stores information about pending IO requests in the transaction table to establish an order among related requests and to permit out-of-order handling of unrelated requests. The IO response handler tracks responses to the IO requests and updates the information in the transaction table. The IO coherence unit returns responses to requesting devices in compliance with device ordering requirements.Type: GrantFiled: March 12, 2008Date of Patent: August 16, 2011Assignee: MIPS Technologies, Inc.Inventors: William Lee, Thomas Benjamin Berg
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Publication number: 20090249046Abstract: A method of coordinating trace information in a multiprocessor system includes receiving processor trace information from a set of processors. The processor trace information from each processor includes a processor identity and a coherence indicator that demarks selective shared memory transactions. Coherence manager trace information is generated for each of the processors. The coherence manager trace information for each processor includes trace metrics and a coherence indicator.Type: ApplicationFiled: March 31, 2008Publication date: October 1, 2009Applicant: MIPS TECHNOLOGIES, INC.Inventors: Thomas Benjamin BERG, Ryan C. KINTER, Jaidev Prasad PATWARDHAN, Radhika THEKKATH
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Publication number: 20090249045Abstract: A computer readable storage medium includes executable instructions to characterize a coherency controller. The executable instructions define ports to receive processor trace information from a set of processors. The processor trace information from each processor includes a processor identity and a condensed coherence indicator. Circuitry produces a trace stream with trace metrics and condensed coherence indicators.Type: ApplicationFiled: March 31, 2008Publication date: October 1, 2009Applicant: MIPS TECHNOLOGIES, INC.Inventors: Thomas Benjamin BERG, Ryan C. KINTER, Jaidev Prasad PATWARDHAN, Radhika THEKKATH
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Publication number: 20090248988Abstract: A multi-core microprocessor includes, in part, a cache coherence manager that maintains coherence among the multitude of microprocessor cores, and an I/O coherence unit that maintains coherent traffic between the I/O devices and the multitude of processing cores of the microprocessor. The I/O coherence unit stalls non-coherent I/O write requests until it receives acknowledgement that all pending coherent I/O write requests issued prior to the non-coherence I/O write requests have been made visible to the processing cores. The I/O coherence unit ensures that MMIO read responses are not delivered to the processing cores until after all previous I/O write requests are made visible to the processing cores. Deadlock conditions are prevented by limiting MMIO requests in such a way that they can never block I/O write requests from completing.Type: ApplicationFiled: March 28, 2008Publication date: October 1, 2009Applicant: MIPS Technologies, Inc.Inventors: Thomas Benjamin Berg, William Lee
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Publication number: 20090234987Abstract: A system, apparatus and method for managing input/output requests in a multi-processor system is disclosed. An IO coherence unit includes an IO request handler, a variable size transaction table, and an IO response handler. The size of the transaction table varies according to the number of pending IO requests. The IO request handler stores information about pending IO requests in the transaction table to establish an order among related requests and to permit out-of-order handling of unrelated requests. The IO response handler tracks responses to the IO requests and updates the information in the transaction table. The IO coherence unit returns responses to requesting devices in compliance with device ordering requirements.Type: ApplicationFiled: March 12, 2008Publication date: September 17, 2009Applicant: MIPS Technologies, Inc.Inventors: William Lee, Thomas Benjamin Berg
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Publication number: 20090089510Abstract: A cache coherence manager, disposed in a multi-core microprocessor, includes a request unit, an intervention unit, a response unit and an interface unit. The request unit receives coherent requests and selectively issues speculative requests in response. The interface unit selectively forwards the speculative requests to a memory. The interface unit includes at least three tables. Each entry in the first table represents an index to the second table. Each entry in the second table represents an index to the third table. The entry in the first table is allocated when a response to an associated intervention message is stored in the first table but before the speculative request is received by the interface unit. The entry in the second table is allocated when the speculative request is stored in the interface unit. The entry in the third table is allocated when the speculative request is issued to the memory.Type: ApplicationFiled: September 28, 2007Publication date: April 2, 2009Applicant: MIPS Technologies, Inc.Inventors: William Lee, Thomas Benjamin Berg