Patents by Inventor Thomas Bonifield
Thomas Bonifield has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961879Abstract: An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.Type: GrantFiled: May 1, 2023Date of Patent: April 16, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jeffrey West, Mrinal Das, Byron Williams, Thomas Bonifield, Maxim Franke
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Publication number: 20230268377Abstract: An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.Type: ApplicationFiled: May 1, 2023Publication date: August 24, 2023Inventors: Jeffrey West, Mrinal Das, Byron Williams, Thomas Bonifield, Maxim Franke
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Patent number: 11688760Abstract: An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.Type: GrantFiled: August 23, 2021Date of Patent: June 27, 2023Assignee: Texas Instruments IncorporatedInventors: Jeffrey West, Mrinal Das, Byron Williams, Thomas Bonifield, Maxim Franke
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Publication number: 20230058511Abstract: An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.Type: ApplicationFiled: August 23, 2021Publication date: February 23, 2023Inventors: Jeffrey West, Mrinal Das, Byron Williams, Thomas Bonifield, Maxim Franke
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Patent number: 7402514Abstract: An embodiment of the instant invention is a method of providing a connection between a first conductor and a second conductor wherein the first conductor is situated under the second conductor and separated by a first insulating layer, the method comprising the steps of: forming an opening in the first insulating layer (layer 124 or 128 of FIGS. 1-4), the opening having a top, a bottom and sidewalls and is situated between the first conductor and the second conductor; forming a second insulating layer (layer 134, 138, and 142 of FIGS. 3 and 4) exclusively on the sidewalls of the opening thereby leaving a smaller opening in the first insulating layer; forming a conductive material (material 140 of FIGS. 3 and 4) in the smaller opening; and wherein the first insulating layer is comprised of a low-k material and the second insulating layer is comprised of an insulator which has electrical leakage properties which are less than the electrical leakage properties of the first insulating layer.Type: GrantFiled: January 24, 2003Date of Patent: July 22, 2008Assignee: Texas Instruments IncorporatedInventors: Robert Tsu, Joe W. McPherson, William R. McKee, Thomas Bonifield
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Publication number: 20070141840Abstract: The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) located over the substrate (110), the nickel silicide region (170) having an amount of indium located therein.Type: ApplicationFiled: February 26, 2007Publication date: June 21, 2007Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Peijun Chen, Duofeng Yue, Amitabh Jain, Sue Crank, Thomas Bonifield, Homi Mogul
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Publication number: 20070049022Abstract: The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.Type: ApplicationFiled: October 20, 2006Publication date: March 1, 2007Applicant: Texas Instruments, IncorporatedInventors: Peijun Chen, Duofeng Yue, Amitabh Jain, Sue Crank, Thomas Bonifield, Homi Mogul
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Publication number: 20060223295Abstract: The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) located over the substrate (110), the nickel silicide region (170) having an amount of indium located therein.Type: ApplicationFiled: April 1, 2005Publication date: October 5, 2006Applicant: Texas Instruments, IncorporatedInventors: Peijun Chen, Duofeng Yue, Amitabh Jain, Sue Crank, Thomas Bonifield, Homi Mogul
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Publication number: 20060024935Abstract: The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises implanting small atoms into an nMOS semiconductor substrate (130) to a depth (132) no greater than about 30 nanometers into the nMOS semiconductor substrate. The method further comprises depositing a transition metal layer (400) over the nMOS semiconductor substrate. The transition metal layer and the nMOS semiconductor substrate are reacted to form the metal silicide electrode. Other aspects of the present invention include a method of manufacturing an integrated circuit (700).Type: ApplicationFiled: July 30, 2004Publication date: February 2, 2006Applicant: Texas Instruments IncorporatedInventors: Duofeng Yue, Peijun Chen, Sue Crank, Thomas Bonifield, Jiong-Ping Lu, Jie-Jie Xu
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Publication number: 20060024938Abstract: The present invention provides a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit including the semiconductor device, and a semiconductor device. The method for manufacturing a semiconductor device, among other steps, includes forming source/drain regions (290) in a substrate (210), the source/drain regions (290) located proximate a gate structure having sidewall spacers (270) and positioned over the substrate (210), and modifying a footprint of the sidewall spacers (270) by forming protective regions (410) proximate a base of the sidewall spacers (270). The method further includes forming metal silicide regions (610) in the source/drain regions (290).Type: ApplicationFiled: July 29, 2004Publication date: February 2, 2006Applicant: Texas Instruments, IncorporatedInventors: Duofeng Yue, Peijun Chen, Jiong-Ping Lu, Thomas Bonifield, Noel Russell
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Publication number: 20060024882Abstract: The present invention provides a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit including the semiconductor devices. The method for manufacturing a semiconductor device (100) , among other steps, includes forming a gate structure (120) over a substrate (110) and forming source/drain regions (190) in the substrate (110) proximate the gate structure (120). The method further includes subjecting the gate structure (120) and substrate (110) to a dry etch process and placing fluorine in the source/drain regions to form fluorinated source/drains (320) subsequent to subjecting the gate structure (120) and substrate (110) to the dry etch process. Thereafter, the method includes forming metal silicide regions (510, 520) in the gate structure (120) and the fluorinated source/drains (320).Type: ApplicationFiled: July 29, 2004Publication date: February 2, 2006Applicant: Texas Instruments, IncorporatedInventors: Jiong-Ping Lu, Clint Montgomery, Lindsey Hall, Donald Miles, Duofeng Yue, Thomas Bonifield
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Publication number: 20040147112Abstract: An embodiment of the instant invention is a method of providing a connection between a first conductor and a second conductor wherein the first conductor is situated under the second conductor and separated by a first insulating layer, the method comprising the steps of: forming an opening in the first insulating layer (layer 124 or 128 of FIGS. 1-4), the opening having a top, a bottom and sidewalls and is situated between the first conductor and the second conductor; forming a second insulating layer (layer 134, 138, and 142 of FIGS. 3 and 4) exclusively on the sidewalls of the opening thereby leaving a smaller opening in the first insulating layer; forming a conductive material (material 140 of FIGS. 3 and 4) in the smaller opening; and wherein the first insulating layer is comprised of a low-k material and the second insulating layer is comprised of an insulator which has electrical leakage properties which are less than the electrical leakage properties of the first insulating layer.Type: ApplicationFiled: January 24, 2003Publication date: July 29, 2004Inventors: Robert Tsu, Joe W. McPherson, William R. McKee, Thomas Bonifield