Patents by Inventor Thomas Boonstra

Thomas Boonstra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240108691
    Abstract: Provided herein are methods of treating a hepatitis E virus (HEV) infection in a human patient are provided. The methods comprise administering to the patient a therapeutically effective amount of interferon lambda.
    Type: Application
    Filed: November 30, 2021
    Publication date: April 4, 2024
    Applicants: Eiger Biopharmaceuticals, Inc., Erasmus MC
    Inventors: Andre Boonstra, Thomas Vanwolleghem, Gulce Sari
  • Patent number: 8705212
    Abstract: An apparatus and associated method may be used to produce a magnetic element capable of detecting changes in magnetic states. Various embodiments of the present invention are generally directed to a magnetically responsive lamination of layers with a first portion and a laterally adjacent second portion. The second portion having a predetermined roughness between at least two layers capable of producing orange-peel coupling.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: April 22, 2014
    Assignee: Seagate Technology LLC
    Inventors: Jason Bryce Gadbois, Michael Christopher Kautzky, Mark William Covington, Dian Song, Dimitar Velikov Dimitrov, Qing He, Wei Tian, Thomas Boonstra, Sunita Gangopadhyay
  • Publication number: 20120268846
    Abstract: An apparatus and associated method may be used to produce a magnetic element capable of detecting changes in magnetic states. Various embodiments of the present invention are generally directed to a magnetically responsive lamination of layers with a first portion and a laterally adjacent second portion. The second portion having a predetermined roughness between at least two layers capable of producing orange-peel coupling.
    Type: Application
    Filed: April 25, 2011
    Publication date: October 25, 2012
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Jason Bryce Gadbois, Michael Christopher Kautzky, Mark William Covington, Dian Song, Dimitar Velikov Dimitrov, Qing He, Wei Tian, Thomas Boonstra, Sunita Gangopadhyay
  • Patent number: 6518591
    Abstract: Methods for monitoring defects in a process for forming a contact hole, via or trench in a layer of a device in an integrated circuit includes the steps of forming a sacrificial topology on a substrate by duplicating at least a portion of a structure of the device while substituting a material substantially free of elemental silicon for any elemental silicon present in the device to be monitored, etching the sacrificial topology at least to the substrate, removing at least a portion of the sacrificial topology, and inspecting the substrate using a wafer surface inspection tool. The substituted material, such as a dielectric material, can be easily etched and removed from the substrate, as compared to polysilicon. The etching step preferably creates an indentation in the substrate that is readily detectable by the wafer surface inspection tool. The etching step is preferably a selective etching step, having a selectivity of at least 10:1.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: February 11, 2003
    Assignee: Cypress Semiconductor Corporation
    Inventors: Edward M. Shamble, Thomas Boonstra, David J. Brownell, David A. Crow
  • Patent number: 6121156
    Abstract: Methods for monitoring defects in a process for forming a contact hole, via or trench in a layer of a device in an integrated circuit includes the steps of forming a sacrificial topology on a substrate by duplicating at least a portion of a structure of the device while substituting a material substantially free of elemental silicon for any elemental silicon present in the device to be monitored, etching the sacrificial topology at least to the substrate, removing at least a portion of the sacrificial topology, and inspecting the substrate using a wafer surface inspection tool. The substituted material, such as a dielectric material, can be easily etched and removed from the substrate, as compared to polysilicon. The etching step preferably creates an indentation in the substrate that is readily detectable by the wafer surface inspection tool. The etching step is preferably a selective etching step, having a selectivity of at least 10:1.
    Type: Grant
    Filed: December 2, 1998
    Date of Patent: September 19, 2000
    Assignee: Cypress Semiconductor Corporation
    Inventors: Edward M. Shamble, Thomas Boonstra, David J. Brownell, David A. Crow