Abstract: A Functional Safety Counter Module is provided and it comprises input circuitry, test circuitry, a first microcontroller including a first hardware counter, a second hardware counter, a first storage device that stores a first firmware algorithm code to execute a counter pattern test in order to detect a short open input signal and/or a failure in counting capability of the first microcontroller and a second microcontroller including a third hardware counter, a fourth hardware counter, a second storage device that stores a second firmware algorithm code. The first and second firmware algorithm codes are configured to resynchronize and restore respectively a first counter or a second counter after the counter pattern test and are configured to detect an offset and adjust during a resynchronization process to account for the offset such that to successfully resynchronize two separate resynchronization algorithm codes are used depending on an input frequency of counter signals input to four hardware counters.

Abstract: The disclosed embodiments relate to simulation of multiple PLCs which are to be physically implemented in a networked or otherwise coordinated manner, such as to control various industrial machines and/or implement multiple steps used in performing an industrial process. Each simulated PLC 114 is throttled relative to each of the other simulated PLCs 114 by use of a common simulated clock 116. The physical characteristics of the particular PLC being simulated are used to ensure that each PLC's behavior is consistent with the physical characteristics of the other PLCs being simulated, e.g. relative to the time elapsed by the common simulated clock 116. Accordingly, simulation of a PLC having physical characteristics different from one or more of the other PLCs will reflect the differences and provide a more accurate representation of the expected actual operation thereof.