Abstract: The invention relates to a multilayer composite, containing a first polymeric layer which on a side is coated with a printing ink containing a polyurethane as binder, and a second layer which with a polyurethane dispersion as adhesive is joined at least partly with the side of the first polymeric layer which is coated with the printing ink containing a polyurethane as binder.

Abstract: The invention relates to a process for decolorizing a composition comprising a betaine comprising the steps of (a) providing a solution of the composition in an organic solvent, (b) contacting the solution with a decolorant, wherein the decolorant is a polar solid decolorant. The invention also relates to uses of ion exchange materials and decolorized solutions and compositions obtainable by the inventive process.

Abstract: The invention relates to a process for decolorizing a composition comprising a betaine comprising the steps of (a) providing a solution of the composition in an organic solvent, (b) contacting the solution with a decolorant, wherein the decolorant is a polar solid decolorant. The invention also relates to uses of ion exchange materials and decolorized solutions and compositions obtainable by the inventive process.

Abstract: The invention relates to a process for the production of L-carnitine tartrate, wherein the L-carnitine tartrate is precipitated from a reaction mixture comprising L-carnitine and tartaric acid dissolved in ethanol, the ethanol having a water content of less than 5% (w/w).

Abstract: A method comprises determining gate configuration from a standard cell library for optimizing behavior of a logic gate in an electronic circuit to be resized. The determining includes defining variables for the logic gate to be resized and defining nets influenced by the logic gate to be resized. The determining includes determining constraints relative to other logic gates in the electronic circuit affected by the logic gate to be resized and formulating objective function. The determining includes solving the objective function using a linear programming solver based on the defined variables and the determined constraints. The determining includes outputting solving of the objective function obtained by linear programming solver for further processing. The gate configuration is selected from the standard cell library for optimizing behavior of the logic gate to be resized based on solving of the objective function.

Abstract: A method comprises estimating power consumption of an electronic circuit. The estimating includes assigning a first gate of the at least one gate into a priority queue based on a levelized result of the electronic circuit for a full circuit calculation and assigning a second gate of the at least one gate into the priority queue which fan-out gate is directly connected to a fan-in gate of a resized gate for an incremental circuit calculation. The estimating includes, for each gate from the priority queue, performing the following operations. Latest and earliest signal arrival times at an output net of the gate are determined by static timing analysis and calculating a glitch window as difference, and a transition metric is calculated for the output net based on the glitch window. The operations include determining an upper bound of signal transitions, and estimating the power consumption based on the upper bound.

Abstract: Subject of the invention is a method for the production of L-carnitine, comprising the steps of (a) providing a solution comprising at least 5% (w/w) carnitine in a first solvent, wherein the carnitine is a mixture of D- and L-carnitine, (b) optionally seeding the solution with L-carnitine crystals, (c) adding an second solvent, in which the L-carnitine is not soluble or has a low solubility, (d) isolating crystals comprising L-carnitine.

Abstract: Additional circuitry is included in an input cell design structure for an integrated circuit to detect and report transitions on an input that was expected to be stable, and to store that event for later analysis. Two or more modified input cells may have their error indications daisy-chained together to minimize additional routing. The storage elements may be included in a scan chain to allow for isolation of which input had the unexpected transition.

Abstract: The invention relates to a voltage regulator circuit for providing voltage to an integrated circuit chip, comprising a reference voltage generator providing a reference voltage, a pFET header device having a plurality of pFET fingers, wherein each pFET finger in the plurality of pFET fingers is adapted for providing a different pFET output voltage to the integrated circuit chip, and a pFET control device for switching the plurality of pFET fingers depending on a comparison between the reference voltage and the pFET output voltage. The voltage regulator circuit allows for dynamically switching on or off the pFET fingers based on the output of the comparison of the reference voltage and the pFET output voltage, and thus allows for dynamically switching on or off, respectively, at least partly the integrated circuit chip.

Abstract: Subject of the invention is a method for the production of a carnitine granulate, which includes the steps of (a) providing an aqueous solution comprising at least 65% (w/w) carnitine, (b) providing a particulate carrier comprising silica, the carrier having an average particle size of more than 150 ?m, and (c) mixing the aqueous solution and the carrier. Another subject of the invention is a carnitine granulate.

Abstract: A method comprises reducing power consumption of an electronic circuit, wherein the electronic circuit comprises at least one logic cone with at least one gate having a single output net, wherein representations of the at least one gate are instances of elements from a standard cell library. Reducing of the power consumption comprises determining an upper bound for dynamic power consumption by calculating transition metrics and power metrics for each gate. Reducing of the power consumption comprises selecting gates with an upper bound for power consumption greater than a predetermined threshold value.

Abstract: A method comprises reducing power consumption of an electronic circuit, wherein the electronic circuit comprises at least one logic cone with at least one gate having a single output net, wherein representations of the at least one gate are instances of elements from a standard cell library. Reducing of the power consumption comprises determining an upper bound for dynamic power consumption by calculating transition metrics and power metrics for each gate. Reducing of the power consumption comprises selecting gates with an upper bound for power consumption greater than a predetermined threshold value.

Abstract: A method comprises determining gate configuration from a standard cell library for optimizing behavior of a logic gate in an electronic circuit to be resized. The determining includes defining variables for the logic gate to be resized and defining nets influenced by the logic gate to be resized. The determining includes determining constraints relative to other logic gates in the electronic circuit affected by the logic gate to be resized and formulating objective function to be solved by the electronic circuit. The determining includes solving the objective function using a linear programming solver based on the defined variables and the determined constraints. The determining includes outputting solving of the objective function obtained by linear programming solver for further processing. The gate configuration is selected from the standard cell library for optimizing behavior of the logic gate to be resized based on solving of the objective function.

Abstract: A method comprises estimating power consumption of an electronic circuit. The estimating includes assigning a first gate of the at least one gate into a priority queue based on a levelized result of the electronic circuit for a full circuit calculation and assigning a second gate of the at least one gate into the priority queue which fan-out gate is directly connected to a fan-in gate of a resized gate for an incremental circuit calculation. The estimating includes, for each gate from the priority queue, performing the following operations. Latest and earliest signal arrival times at an output net of the gate are determined by static timing analysis and calculating a glitch window as difference, and a transition metric is calculated for the output net based on the glitch window. The operations include determining an upper bound of signal transitions, and estimating the power consumption based on the upper bound.

Abstract: A fermentation device for biological degradation of substrate containing organic material and for recovery of biogas produced by degradation has an elongate closed container having a first end and a second end opposite the first end. The first end has an inlet opening for untreated substrate and the second end has at least one removal opening for treated substrate. The container has at least one removal opening for biogas. The container has several reaction cells provided with individually driven mixing units. The mixing units have mixing unit shafts positioned transversely to a longitudinal extension of the container and mixing impellers mounted on the mixing unit shafts and driven on a circular path. The mixing unit shafts are arranged at axial spacings smaller than a diameter of the mixing units so that the mixing impellers when the mixing unit shafts rotate pass trough an overlap range.

Abstract: Additional circuitry is included in an input cell design structure for an integrated circuit to detect and report transitions on an input that was expected to be stable, and to store that event for later analysis. Two or more modified input cells may have their error indications daisy-chained together to minimize additional routing. The storage elements may be included in a scan chain to allow for isolation of which input had the unexpected transition.

Abstract: The invention relates to a voltage regulator circuit for providing voltage to an integrated circuit chip, comprising a reference voltage generator providing a reference voltage, a pFET header device having a plurality of pFET fingers, wherein each pFET finger in the plurality of pFET fingers is adapted for providing a different pFET output voltage to the integrated circuit chip, and a pFET control device for switching the plurality of pFET fingers depending on a comparison between the reference voltage and the pFET output voltage. The voltage regulator circuit allows for dynamically switching on or of the pFET fingers based on the output of the comparison of the reference voltage and the pFET output voltage, and thus allows for dynamically switching on or off, respectively, at least partly the integrated circuit chip.

Abstract: The invention relates to a process for the production of L-carnitine tartrate, wherein the L-carnitine tartrate is precipitated from a reaction mixture comprising L-carnitine and tartaric acid dissolved in ethanol, the ethanol having a water content of less than 5% (w/w).

Abstract: Subject of the invention is a method for the production of a carnitine granulate, which includes the steps of (a) providing an aqueous solution comprising at least 65% (w/w) carnitine, (b) providing a particulate carrier comprising silica, the carrier having an average particle size of more than 150 ?m, and (c) mixing the aqueous solution and the carrier. Another subject of the invention is a carnitine granulate.

Abstract: Subject of the invention is a method for the production of L-carnitine, comprising the steps of (a) providing a solution comprising at least 5% (w/w) carnitine in a first solvent, wherein the carnitine is a mixture of D- and L-carnitine, (b) optionally seeding the solution with L-carnitine crystals, (c) adding an second solvent, in which the L-carnitine is not soluble or has a low solubility, (d) isolating crystals comprising L-carnitine.