Abstract: The invention relates to a process for the production of L-carnitine tartrate, wherein the L-carnitine tartrate is precipitated from a reaction mixture comprising L-carnitine and tartaric acid dissolved in ethanol, the ethanol having a water content of less than 5% (w/w).

Abstract: A method comprises determining gate configuration from a standard cell library for optimizing behavior of a logic gate in an electronic circuit to be resized. The determining includes defining variables for the logic gate to be resized and defining nets influenced by the logic gate to be resized. The determining includes determining constraints relative to other logic gates in the electronic circuit affected by the logic gate to be resized and formulating objective function. The determining includes solving the objective function using a linear programming solver based on the defined variables and the determined constraints. The determining includes outputting solving of the objective function obtained by linear programming solver for further processing. The gate configuration is selected from the standard cell library for optimizing behavior of the logic gate to be resized based on solving of the objective function.

Abstract: A method comprises estimating power consumption of an electronic circuit. The estimating includes assigning a first gate of the at least one gate into a priority queue based on a levelized result of the electronic circuit for a full circuit calculation and assigning a second gate of the at least one gate into the priority queue which fan-out gate is directly connected to a fan-in gate of a resized gate for an incremental circuit calculation. The estimating includes, for each gate from the priority queue, performing the following operations. Latest and earliest signal arrival times at an output net of the gate are determined by static timing analysis and calculating a glitch window as difference, and a transition metric is calculated for the output net based on the glitch window. The operations include determining an upper bound of signal transitions, and estimating the power consumption based on the upper bound.

Abstract: Additional circuitry is included in an input cell design structure for an integrated circuit to detect and report transitions on an input that was expected to be stable, and to store that event for later analysis. Two or more modified input cells may have their error indications daisy-chained together to minimize additional routing. The storage elements may be included in a scan chain to allow for isolation of which input had the unexpected transition.

Abstract: The invention relates to a voltage regulator circuit for providing voltage to an integrated circuit chip, comprising a reference voltage generator providing a reference voltage, a pFET header device having a plurality of pFET fingers, wherein each pFET finger in the plurality of pFET fingers is adapted for providing a different pFET output voltage to the integrated circuit chip, and a pFET control device for switching the plurality of pFET fingers depending on a comparison between the reference voltage and the pFET output voltage. The voltage regulator circuit allows for dynamically switching on or off the pFET fingers based on the output of the comparison of the reference voltage and the pFET output voltage, and thus allows for dynamically switching on or off, respectively, at least partly the integrated circuit chip.

Abstract: A method comprises reducing power consumption of an electronic circuit, wherein the electronic circuit comprises at least one logic cone with at least one gate having a single output net, wherein representations of the at least one gate are instances of elements from a standard cell library. Reducing of the power consumption comprises determining an upper bound for dynamic power consumption by calculating transition metrics and power metrics for each gate. Reducing of the power consumption comprises selecting gates with an upper bound for power consumption greater than a predetermined threshold value.

Abstract: A method comprises reducing power consumption of an electronic circuit, wherein the electronic circuit comprises at least one logic cone with at least one gate having a single output net, wherein representations of the at least one gate are instances of elements from a standard cell library. Reducing of the power consumption comprises determining an upper bound for dynamic power consumption by calculating transition metrics and power metrics for each gate. Reducing of the power consumption comprises selecting gates with an upper bound for power consumption greater than a predetermined threshold value.

Abstract: A method comprises determining gate configuration from a standard cell library for optimizing behavior of a logic gate in an electronic circuit to be resized. The determining includes defining variables for the logic gate to be resized and defining nets influenced by the logic gate to be resized. The determining includes determining constraints relative to other logic gates in the electronic circuit affected by the logic gate to be resized and formulating objective function to be solved by the electronic circuit. The determining includes solving the objective function using a linear programming solver based on the defined variables and the determined constraints. The determining includes outputting solving of the objective function obtained by linear programming solver for further processing. The gate configuration is selected from the standard cell library for optimizing behavior of the logic gate to be resized based on solving of the objective function.

Abstract: A method comprises estimating power consumption of an electronic circuit. The estimating includes assigning a first gate of the at least one gate into a priority queue based on a levelized result of the electronic circuit for a full circuit calculation and assigning a second gate of the at least one gate into the priority queue which fan-out gate is directly connected to a fan-in gate of a resized gate for an incremental circuit calculation. The estimating includes, for each gate from the priority queue, performing the following operations. Latest and earliest signal arrival times at an output net of the gate are determined by static timing analysis and calculating a glitch window as difference, and a transition metric is calculated for the output net based on the glitch window. The operations include determining an upper bound of signal transitions, and estimating the power consumption based on the upper bound.

Abstract: Additional circuitry is included in an input cell design structure for an integrated circuit to detect and report transitions on an input that was expected to be stable, and to store that event for later analysis. Two or more modified input cells may have their error indications daisy-chained together to minimize additional routing. The storage elements may be included in a scan chain to allow for isolation of which input had the unexpected transition.

Abstract: The invention relates to a voltage regulator circuit for providing voltage to an integrated circuit chip, comprising a reference voltage generator providing a reference voltage, a pFET header device having a plurality of pFET fingers, wherein each pFET finger in the plurality of pFET fingers is adapted for providing a different pFET output voltage to the integrated circuit chip, and a pFET control device for switching the plurality of pFET fingers depending on a comparison between the reference voltage and the pFET output voltage. The voltage regulator circuit allows for dynamically switching on or of the pFET fingers based on the output of the comparison of the reference voltage and the pFET output voltage, and thus allows for dynamically switching on or off, respectively, at least partly the integrated circuit chip.

Abstract: The invention relates to a process for the production of L-carnitine tartrate, wherein the L-carnitine tartrate is precipitated from a reaction mixture comprising L-carnitine and tartaric acid dissolved in ethanol, the ethanol having a water content of less than 5% (w/w).

Abstract: A method and a device for supplying power to one or more microelectronic chips. The method comprises the steps of reading a process characteristic parameter associated with the chip from a non-volatile storage, wherein the process characteristic parameter represents a manufacturing process characteristics of the chip; determining a minimal voltage (VDD_min) based on the parameter; and supplying electric power to the chip (10) with the minimal voltage (VDD_min). The device includes a hardware portion, and a firmware portion wherein the firmware portion includes a unit for determining a minimal voltage (VDD_min) based on a process characteristic parameter of the one or more chips.

Abstract: A method and circuits for monitoring and detecting an error in the static pervasive signals applied to input/output pins of an integrated circuit during functional operation of the integrated circuit. The method and circuits provide a signal signature of each of one or more groups of the static pervasive signals and then monitoring the signal signature for any change of logic level.

Abstract: A method and circuits for monitoring and detecting an error in the static pervasive signals applied to input/output pins of an integrated circuit during functional operation of the integrated circuit. The method and circuits provide a signal signature of each of one or more groups of the static pervasive signals and then monitoring the signal signature for any change of logic level.

Abstract: A process and a device for biological treatment of a suspension in a bioreactor (2) are described. To circulate the suspension, at least some of the suspension is routed through a vertically aligned guide zone (5) so that a vertical flow of the suspension is produced. To control sediment problems, it is suggested that by feeding a fluid, especially a free liquid jet, via at least one nozzle (11), a horizontal flow is superimposed on the vertical flow in the vicinity of the bottom of the bioreactor (2), by which a spiral flow to the central outlet area of the bioreactor (2) is produced (FIG. 1).

Abstract: A process and a device for biological treatment of a suspension in a bioreactor, wherein the suspension is circulated, at least some of the suspension is routed through a vertically aligned guide zone in the bioreactor so that a vertical flow of the suspension is produced. The top scum in the area of the suspension fill level is controlled by feeding a fluid, especially in the form of a free liquid jet, into the bioreactor via at least one nozzle at the fill level, such that the surface of the suspension and/or the top scum floating on the surface of the suspension is forced into rotary flow.

Abstract: A process and a device for biological treatment of a suspension in a bioreactor (2) are described. To circulate the suspension, at least some of the suspension is routed through a vertically aligned guide zone (5) so that a vertical flow of the suspension is produced. To control sediment problems, it is suggested that by feeding a fluid, especially a free liquid jet, via at least one nozzle (11), a horizontal flow is superimposed on the vertical flow in the vicinity of the bottom of the bioreactor (2), by which a spiral flow to the central outlet area of the bioreactor (2) is produced (FIG. 1).

Abstract: A non-obtrusive activity monitor is proposed for advantageously monitoring and tracing disjunct, concurrent computer system operations in heavily queued computer systems. For each traced and pending computer system operation, the monitor uses a hardware implementation of an event triggered operation graph to trace the path of the computer system operation through the computer system. For each followed path, a unique signature is generated that significantly reduces the amount of trace data to be stored. In a preferred embodiment, the trace information is stored together with a time stamp for debugging and measuring queuing effects and timing behavior in a computer system.

Abstract: A process and a device for biological treatment of a suspension in a bioreactor, wherein the suspension is circulated, at least some of the suspension is routed through a vertically aligned guide zone in the bioreactor so that a vertical flow of the suspension is produced. The top scum in the area of the suspension fill level is controlled by feeding a fluid, especially in the form of a free liquid jet, into the bioreactor via at least one nozzle at the fill level, such that the surface of the suspension and/or the top scum floating on the surface of the suspension is forced into rotary flow.