Patents by Inventor Thomas C. Cecil
Thomas C. Cecil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11860531Abstract: In certain embodiments, a method includes the following steps. A layout used in a lithographic mask development process is accessed. For example, the layout may be the layout of the mask itself, or it may be the layout of the resulting printed pattern on the wafer. The layout includes a number of disjoint shapes. Skeleton representations for at least some of the disjoint shapes in the layout are determined. The skeleton representation of an individual shape has elements of two or more nodes connected by edges. It also includes size parameters for at least some of the elements. The skeleton representations of the shapes are used in the mask development process.Type: GrantFiled: February 19, 2021Date of Patent: January 2, 2024Assignee: Synopsys, Inc.Inventors: Thomas C. Cecil, David W. Thomas
-
Publication number: 20210255539Abstract: In certain embodiments, a method includes the following steps. A layout used in a lithographic mask development process is accessed. For example, the layout may be the layout of the mask itself, or it may be the layout of the resulting printed pattern on the wafer. The layout includes a number of disjoint shapes. Skeleton representations for at least some of the disjoint shapes in the layout are determined. The skeleton representation of an individual shape has elements of two or more nodes connected by edges. It also includes size parameters for at least some of the elements. The skeleton representations of the shapes are used in the mask development process.Type: ApplicationFiled: February 19, 2021Publication date: August 19, 2021Inventors: Thomas C. Cecil, David W. Thomas
-
Patent number: 10262100Abstract: A method for generating sub-resolution assist features (SRAFs) for target features of a photomask includes generating a 2D rules-based assist feature (RBAF) rules table that estimates results obtained from a model-based SRAF method. The 2D RBAF rules table defines seed skeletons using polar coordinates. Empty space surrounding the target features is divided into corresponding owned regions. Seed skeletons are placed in the owned regions using the 2D RBAF rules table. The seed skeletons are widened, and the resulting structure is re-skeletonized. A cleaning process is performed on the re-skeletonized structure, eliminating potentially troublesome features, including stubs, forks, triple-points and quad-points. The cleaned skeleton structure is straightened, and polygonal SRAFs are placed at locations specified by the straightened skeleton structure.Type: GrantFiled: May 24, 2017Date of Patent: April 16, 2019Assignee: Synopsys, Inc.Inventor: Thomas C. Cecil
-
Publication number: 20180341740Abstract: A method for generating sub-resolution assist features (SRAFs) for target features of a photomask includes generating a 2D rules-based assist feature (RBAF) rules table that estimates results obtained from a model-based SRAF method. The 2D RBAF rules table defines seed skeletons using polar coordinates. Empty space surrounding the target features is divided into corresponding owned regions. Seed skeletons are placed in the owned regions using the 2D RBAF rules table. The seed skeletons are widened, and the resulting structure is re-skeletonized. A cleaning process is performed on the re-skeletonized structure, eliminating potentially troublesome features, including stubs, forks, triple-points and quad-points. The cleaned skeleton structure is straightened, and polygonal SRAFs are placed at locations specified by the straightened skeleton structure.Type: ApplicationFiled: May 24, 2017Publication date: November 29, 2018Inventor: Thomas C. Cecil
-
Patent number: 8498469Abstract: A technique for determining a full-field Mask Error Enhancement Function (MEEF) associated with a mask pattern for use in a photo-lithographic process is described. In this technique, simulated wafer patterns corresponding to the mask pattern are generated at an image plane in an optical path associated with the photo-lithographic process. Then, the full-field MEEF is determined. This full-field MEEF includes MEEF values in multiple directions at positions along one or more contours that define boundaries of one or more features in the one or more simulated wafer patterns. Moreover, at least one of the MEEF values is at a position on a contour where a critical dimension for a feature associated with the contour is undefined.Type: GrantFiled: March 1, 2010Date of Patent: July 30, 2013Assignee: Synopsys, Inc.Inventors: Guangming Xiao, Thomas C. Cecil, Linyong Pang, Robert E. Gleason, John F. McCarty
-
Patent number: 8473878Abstract: During a calculation technique, at least a portion of a target pattern associated with an integrated-circuit design is modified so that polygons in the target pattern, which represent features in the design, result in acceptable accuracy during a photolithographic process that fabricates the target pattern on a semiconductor die. In particular, a set of polygon parameters associated with the polygons are modified, as needed, so that a cost function that corresponds to a difference between a modified target pattern and an estimated target pattern produced during the photolithographic process meets a termination criterion. A mask pattern that can fabricate the modified target pattern on the semiconductor die is calculated using an inverse optical calculation in which the modified target pattern is at an image plane of an optical path associated with the photolithographic process and the mask pattern is at an object plane of the optical path.Type: GrantFiled: November 28, 2011Date of Patent: June 25, 2013Assignee: Synopsys, Inc.Inventors: Tatung Chow, Changqing Hu, Donghwan Son, David H. Kim, Thomas C. Cecil
-
Publication number: 20130139116Abstract: During a calculation technique, at least a portion of a target pattern associated with an integrated-circuit design is modified so that polygons in the target pattern, which represent features in the design, result in acceptable accuracy during a photolithographic process that fabricates the target pattern on a semiconductor die. In particular, a set of polygon parameters associated with the polygons are modified, as needed, so that a cost function that corresponds to a difference between a modified target pattern and an estimated target pattern produced during the photolithographic process meets a termination criterion. A mask pattern that can fabricate the modified target pattern on the semiconductor die is calculated using an inverse optical calculation in which the modified target pattern is at an image plane of an optical path associated with the photolithographic process and the mask pattern is at an object plane of the optical path.Type: ApplicationFiled: November 28, 2011Publication date: May 30, 2013Applicant: Luminescent Technologies, Inc.Inventors: Tatung Chow, Changqing Hu, Donghwan Son, David H. Kim, Thomas C. Cecil
-
Patent number: 8028252Abstract: During a method for generating a third mask pattern to be used on a photo-mask in a photolithographic process, first features are added to a first mask pattern to produce a second mask pattern. A majority of the first features may have a size characteristic larger than a pre-determined value, and that the first features are topologically disconnected from second features in the first mask pattern that overlap third features in a target pattern. Moreover, the first features may be added at positions which are determined based on the gradient of a first cost function depending, at least in part, on the first mask pattern and the target pattern. Then, the third mask pattern may be generated based on the second mask pattern, where the photo-mask corresponds to the third mask pattern.Type: GrantFiled: September 10, 2008Date of Patent: September 27, 2011Assignee: Luminescent Technologies Inc.Inventor: Thomas C. Cecil
-
Publication number: 20110211748Abstract: A technique for determining a full-field Mask Error Enhancement Function (MEEF) associated with a mask pattern for use in a photo-lithographic process is described. In this technique, simulated wafer patterns corresponding to the mask pattern are generated at an image plane in an optical path associated with the photo-lithographic process. Then, the full-field MEEF is determined. This full-field MEEF includes MEEF values in multiple directions at positions along one or more contours that define boundaries of one or more features in the one or more simulated wafer patterns. Moreover, at least one of the MEEF values is at a position on a contour where a critical dimension for a feature associated with the contour is undefined.Type: ApplicationFiled: March 1, 2010Publication date: September 1, 2011Inventors: Guangming Xiao, Thomas C. Cecil, Linyong Pang, Robert E. Gleason, John F. McCarty
-
Publication number: 20090075183Abstract: During a method for generating a third mask pattern to be used on a photo-mask in a photolithographic process, first features are added to a first mask pattern to produce a second mask pattern. A majority of the first features may have a size characteristic larger than a pre-determined value, and that the first features are topologically disconnected from second features in the first mask pattern that overlap third features in a target pattern. Moreover, the first features may be added at positions which are determined based on the gradient of a first cost function depending, at least in part, on the first mask pattern and the target pattern. Then, the third mask pattern may be generated based on the second mask pattern, where the photo-mask corresponds to the third mask pattern.Type: ApplicationFiled: September 10, 2008Publication date: March 19, 2009Inventor: Thomas C. Cecil