Abstract: A graphics data processing system memory is allocatable by software between system memory and graphics framebuffer storage. The memory comprises two-port elements connected in parallel from the RAM port to a controller connected to a bus, and having serial output ports connected to output circuitry to map the storage to a display. Corresponding locations, relative to element origin, in all elements are addressed in parallel as an array. Three modes of memory transactions are all accomplished as array accesses. First, a processor reads/writes the system memory portion by a combination of parallel array access and transfers between controller and bus in successive bus cycles. Second, the controller executes atomic graphics operations on the framebuffer storage using successive array accesses; third, the processor can read/write a framebuffer pixel, by an array access of framebuffer storage with masking of unaddressed pixels. An interface arbitrates among requests for memory access.

Abstract: A method for drawing a convex geometric figure to framebuffer storage uses a plurality of update arrays which tile the framebuffer, each having a determined origin with respect to the framebuffer. Each update array has a multiplicity of concurrently updatable pixel storage sites, each specified by an offset from array origin. A figure is specified by a set of directed segments which form its perimeter. To access only those update arrays which tile the figure, the following methodology is used. A first update array which is known to be part of the figure is accessed. Tests are then performed to find whether the figure extends to arrays above or below the accessed array. If so, the array address is stored and marked for either or both extensions. In one embodiment, a test is performed for left extension, and the steps are repeated until no further left extension is found. Returning to the initial array, the steps are repeated for right extension to complete the horizontal subset.

Abstract: The present circuit arrangement is principally directed to scrolling of a region or regions on a video display and includes a bit map memory, at least one address generation and control signal circuitry chip, one or more data signal path circuitry chips, timing circuitry and logic circuitry interconnecting the foregoing various sections of circuitry. The present arrangement functions to refresh, scroll and update during each horizontal scan, in response to a plurality of timing cycles, with every other cycle being a refresh cycle and the intervening cycles being either scroll or update cycles. During a refresh cycle there is a burst of signals read from memory and transmitted to a shift register feeding the video screen to effect refreshing a section of the screen. At the same time those signals are used to refresh the memory.