Abstract: Instead of alternatively utilizing only one fabric or the other fabric of a redundant pair, both fabrics simultaneously transmit duplicate information, such that each packet forwarding module (PFM) receives the output of both fabrics simultaneously. In real time, an internal optics module (IOM) analyzes each information chunk coming out of a working zero switch fabric; simultaneously examines a parallel output of a working one duplicate switch fabric; and compares on a chunk-by-chunk basis the validity of each and every chunk from both switch fabrics. The IOM does this by examining forward error correction (FEC) check symbols encapsulated into each chunk. FEC check symbols allow correcting a predetermined number of bit errors within a chunk. If the chunk cannot be corrected, then the IOM provides indication to all PFMs downstream that the chunk is defective. Under such conditions, the PFMs select a chunk from the non-defective switch fabric.

Abstract: A chunk format for a large-scale, high data throughput router includes a preamble that allows each individual chunk to have clock and data recovery performed before the chunk data is retrieved. The format includes a chunk header that contains information specific to the entire chunk. A chunk according to the present format can contain multiple packet segments, with each segment having its own packet header for packet-specific information. The format provides for a scrambler seed which allows scrambling the data to achieve a favorable zero and one balance as well as minimal run lengths. There can be a random choice of available scrambler seeds for any particular chunk to avoid malicious forcing of zero and one patterns or run lengths of bit zeroes and ones. There are a chunk cyclical redundancy check (CRC) as well as forward error correction (FEC) bytes to detect and/or correct any errors and also to insure a high degree of data and control integrity.

Abstract: A chunk format for a large-scale, high data throughput router includes a preamble that allows each individual chunk to have clock and data recovery performed before the chunk data is retrieved. The format includes a chunk header that contains information specific to the entire chunk. A chunk according to the present format can contain multiple packet segments, with each segment having its own packet header for packet-specific information. The format provides for a scrambler seed which allows scrambling the data to achieve a favorable zero and one balance as well as minimal run lengths. There are forward error correction (FEC) bytes as well as a chunk cyclical redundancy check (CRC) to detect and/or correct any errors and also to insure a high degree of data and control integrity. Advantageously, a framing symbol inserted into the chunk format itself allows the receiving circuitry to identify or locate a particular chunk format.

Abstract: A router line card is partitioned to separate the packet forwarding functions from physical port interfacing. For each packet forwarding card, at least one redundant port interface is provided. Identical input packets are transmitted via these redundant input port interfaces, one of which is eventually selected based on, for example, SONET standard criteria. If there is a failure, the router selects the interface path that is operating properly and rejects the path containing a failed element. Thus, the router decides locally how to correct the problem internally. Moreover, following an equipment failure the now offline failed interface path can be replaced, while the equipment remains in service using the duplicated interface path. The system can be restored to full duplex operation without affecting the existing traffic, providing for a hot replacement of a failed path. Because the interfaces are separate, a failed module can be renewed and replaced while the equipment is in service.

Abstract: A repetitive burst-mode input signal that has a dark time portion, a preamble portion, and a payload portion is converted into a limited output signal in accordance with a decision threshold level, which is controlled by selectively coupling an averaged value of the burst-mode data amplitude to the decision threshold level. The timing sequence for selectively coupling the averaged signal value is controlled such that the average value of the burst-mode signal acquired during the preamble portion of the burst-mode signal is applied to the decision threshold level during substantially all of the payload portion. The control circuit may incorporate a phase-locked loop, which locks onto the repetitive dark time frequency and in response synthesizes a switchable track enable signal that controls the timing sequence of the decision threshold level. The phase-locked loop can employ all-digital, analog, and/or hybrid digital/analog circuitry.

Abstract: A multicast packet is transferred through a switching fabric from an input line card to a dedicated multicast card, which is substantially the same as an input and output line card, but without external facility interfaces. A dedicated output multicast card converts the multicast packet from an optical to an electrical packet and passes it to a dedicated input multicast card, where the packet is replicated electrically, converted back to an optical packet, and then transferred through the switching fabric to multiple destinations. In some embodiments, input and output dedicated multicast cards are actually a single card. Transfer of the multicast packet to multiple destinations occurs sequentially or simultaneously during a single switching cycle, if multiple parallel switching paths exist through the switching fabric. Some embodiments include multiple dedicated multicast cards, allowing rapid simultaneous expansion of the multicast tree.

Abstract: Instead of alternatively utilizing only one fabric or the other fabric of a redundant pair, both fabrics simultaneously transmit duplicate information, such that each packet forwarding module (PFM) receives the output of both fabrics simultaneously. In real time, an internal optics module (IOM) analyzes each information chunk coming out of a working zero switch fabric; simultaneously examines a parallel output of a working one duplicate switch fabric; and compares on a chunk-by-chunk basis the validity of each and every chunk from both switch fabrics. The IOM does this by examining forward error correction (FEC) check symbols encapsulated into each chunk. FEC check symbols allow correcting a predetermined number of bit errors within a chunk. If the chunk cannot be corrected, then the IOM provides indication to all PFMs downstream that the chunk is defective. Under such conditions, the PFMs select a chunk from the non-defective switch fabric.

Abstract: Router line cards are partitioned, separating packet forwarding from external or internal interfaces and enabling multiple line cards to access any set of external or internal data paths. Any failed working line card can be switchably replaced by another line card. In particular, a serial bus structure on the interface side interconnects any interface port within a protection group with a protect line card for that group. Incremental capacity allows the protect line card to perform packet forward functions. Logical mapping of line card addressing and identification provides locally managed protection switching of a line card that is transparent to other router line cards and to all peer routers. One-for-N protection ratios, where N is some integer greater than two, can be achieved economically, yet provide sufficient capacity with acceptable protection switch time under 100 milliseconds.

Abstract: If each data channel comprising a set of multiplexed data channels contains channel identity information, a single framing detector operating on one channel can provide a framing detection operation regardless of where the search is commenced thereby avoiding a search of all of the channels to obtain framing information. By having unique tag or identity bits incorporated in each of the multiplexed data channels, the timing problems for obtaining synchronized parallel output bits from each of the channels can be logically ascertained and the channels can be rerouted and individual channels of the rerouted channels can be time delayed to obtain the time synchronization.

Abstract: A delay circuit including an even number of memory devices, for example two, reading from one memory device, while writing to the other. Sequences of bit addresses are generated for writing and reading, with an offset between the sequences. For the case of two memory devices, each address sequence is applied alternately to the one and then the other memory device. Importantly, if each memory device has an even number n of storage locations, then, preferably, only (n-1) of these are used in the generated sequences of addresses. This has the result that the circuit can write to and read from all of the memory locations in the memory devices. Thus, the maximum delay possible in the circuit of the invention is nearly the total number of bits in the multiple memory devices, and the circuit is capable of handling data at the maximum operating rate of the memory devices.

Abstract: A clock system is disclosed having two identical clocks not synchronized with each other. Each of the clocks includes a circuit for selecting the output of one of the clocks as the present system output. Further, each clock includes logic for detecting errors in the operation of itself, and of the other. When an error is detected in the operation of the clock selected to be the present system output, a switchover sequence control switches the output signal of the nonselected clock to become the new system output. The switchover sequence control includes a feature which ensures that the interval between pulses in the system output is greater than a predetermined period in order to minimize detrimental effects on circuitry utilizing the clock system output.