Patents by Inventor Thomas C. Perez

Thomas C. Perez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240112060
    Abstract: In a general aspect, a surface code syndrome measurement is performed on a superconducting quantum processing unit. In some implementations, the superconducting quantum processing unit is caused to apply a quantum error correction code including X-type and Z-type stabilizer check patches. Each of the X-type and Z-type stabilizer check patches includes a stabilizer check qubit device and data qubit devices of the superconducting quantum processing unit. Applying the quantum error correction code includes iteratively twirling the data qubit devices in a stabilizer check patch; and evolving the stabilizer check qubit device in the stabilizer check patch and the data qubit devices in the stabilizer check patch under an interaction Hamiltonian. The interaction Hamiltonian includes a plurality of terms interactions between the stabilizer check qubit device in the stabilizer check patch and a respective one of the data qubit devices in the stabilizer check patch.
    Type: Application
    Filed: September 11, 2023
    Publication date: April 4, 2024
    Applicants: Rigetti & Co, LLC, Goldman Sachs & Co. LLC
    Inventors: Matthew J. Reagor, Thomas C. Bohdanowicz, David Rodriguez Perez, Eyob A. Sete, William J. Zeng
  • Patent number: 8713485
    Abstract: Embodiments of the invention include a method for categorizing and displaying design rule errors. The method may include receiving, from a design rule checker, more than one violation of a design rule within a design layout. The method may also include determining distinct categories of the design rule violations by comparing parameters associated with the design rule violations.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: April 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Richard S. Brink, Michael R. Curry, Jay A. Lawrence, Thomas C. Perez, Scott Trcka, John W. Zack
  • Publication number: 20130326445
    Abstract: Embodiments of the invention include a method for categorizing and displaying design rule errors. The method may include receiving, from a design rule checker, more than one violation of a design rule within a design layout. The method may also include determining distinct categories of the design rule violations by comparing parameters associated with the design rule violations.
    Type: Application
    Filed: May 29, 2012
    Publication date: December 5, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Richard S. Brink, Michael R. Curry, Jay A. Lawrence, Thomas C. Perez, Scott Trcka, John W. Zack
  • Publication number: 20120254816
    Abstract: A computer implemented method, system, and/or computer program product reduce noise in a circuit. A level of noise imposed by an aggressor line on a victim line is determined. The aggressor line and the victim line are an aggressor/victim line pair from multiple aggressor/victim line pairs in a circuit. Determination of the noise level is conducted during a predetermined window of time during which a signal is being transmitted along the aggressor line. Each of the multiple aggressor/victim line pairs are ranked according to a level of noise being imposed by each aggressor line on each victim line. The spacing between a highest ranked aggressor/victim line pair is then expanded.
    Type: Application
    Filed: April 1, 2011
    Publication date: October 4, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: RICHARD S. BRINK, MICHAEL R. CURRY, DONALD R. FEARN, MICHAEL D. MAURICE, THOMAS C. PEREZ, SCOTT TRCKA, JOHN W. ZACK
  • Publication number: 20090064075
    Abstract: A method and apparatus for displaying hierarchical navigation and editing a plurality of hierarchical levels of design of an integrated circuit includes opening a main editor screen, displaying a viewable scope of hierarchical levels of design in the main editor screen and using a computer to assign a side window adjacent to the main editor screen. The side-window displays information about schematics previously viewed including thumbnail views of most recently viewed levels of the plurality of hierarchical levels of design. Using the computer input device, the user scrolls through the main editor screen into a hierarchical level of design. The side window is populated with a schematic that was last viewed and a thumbnail view of the hierarchical level of design is surrounded by a highlighted border, enabling the user to view schematic elements underneath the hierarchical level of design and to see the thumbnail view of the top-level schematic.
    Type: Application
    Filed: August 28, 2007
    Publication date: March 5, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Blaine J. Gross, Karl L. Ladin, Thomas C. Perez
  • Publication number: 20080320429
    Abstract: A computer program product stored on machine readable media including machine executable instructions for display a layout of a circuit design, includes instructions for: receiving designation of at least one design segment from a user; receiving designation of a degree of intensity for at least one of highlighting and dimming the design segments and on a display screen, highlighting the designated design segments and dimming remaining segments on the display. A system is also provided.
    Type: Application
    Filed: June 21, 2007
    Publication date: December 25, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Blaine J. Gross, Karl L. Ladin, Thomas C. Perez