Patents by Inventor Thomas C. Poff

Thomas C. Poff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9098297
    Abstract: An apparatus and method are provided including a hardware accelerator capable of being interfaced with a processor for accelerating the execution of an application written utilizing an object-oriented programming language. Such object-oriented programming language may include Java and/or C++.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: August 4, 2015
    Assignee: NVIDIA Corporation
    Inventors: Thomas C. Poff, John Shigeto Minami, Ryo Koyama
  • Patent number: 6983357
    Abstract: A method and apparatus for accelerating an object-oriented programming language are provided at a hardware gate level. In a Java-compliant embodiment, a Java Application framework is implemented in hardware. The Java.AWT, Java.NET. and Java.IO application frameworks are supported in the preferred embodiment of the invention. Instances and methods of supported application framework classes that are executed by a Java program are offloaded to a hardware object management system. A software stub is provided as an interface between the hardware object management system and the central processing unit.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: January 3, 2006
    Assignee: NVIDIA Corporation
    Inventors: Thomas C. Poff, John Shigeto Minami, Ryo Koyama
  • Publication number: 20020078115
    Abstract: A method and apparatus for accelerating an object-oriented programming language are provided at a hardware gate level. In a Java-compliant embodiment, a Java Application framework is implemented in hardware. The Java.AWT, Java.NET, and Java.IO application frameworks are supported in the preferred embodiment of the invention. Application framework classes are stored as libraries in a shared memory. Instances and methods of supported application framework classes that are executed by a Java program are offloaded to a hardware object management system. A software stub is provided as an interface between the hardware object management system and the central processing unit. Additional application frameworks can be supported by modifying or replacing the software stub. Hardware object management system requests are executed by an application framework-specific hardware accelerator.
    Type: Application
    Filed: June 20, 2001
    Publication date: June 20, 2002
    Inventors: Thomas C. Poff, John Shigeto Minami, Ryo Koyama
  • Patent number: 6330659
    Abstract: A method and apparatus for accelerating an object-oriented programming language are provided at a hardware gate level. In a Java-compliant embodiment, a Java Application framework is implemented in hardware. The Java.AWT, Java.NET, and Java.IO application frameworks are supported in the preferred embodiment of the invention. Application framework classes are stored as libraries in a shared memory. Instances and methods of supported application framework classes that are executed by a Java program are offloaded to a hardware object management system. A software stub is provided as an interface between the hardware object management system and the central processing unit. Central processing unit processing of non-supported application framework instructions is continued during hardware accelerator execution of hardware object management system requests.
    Type: Grant
    Filed: November 6, 1997
    Date of Patent: December 11, 2001
    Assignee: iReady Corporation
    Inventors: Thomas C. Poff, John Shigeto Minami, Ryo Koyama
  • Patent number: 6034963
    Abstract: A multiple network protocol encoder/decoder comprising a network protocol layer, data handler, O.S. State machine, and memory manager state machines implemented at a hardware gate level. Network packets are received from a physical transport level mechanism by the network protocol layer state machine which decodes network protocols such as TCP, IP, User Datagram Protocol (UDP), PPP, and Raw Socket concurrently as each byte is received. Each protocol handler parses and strips header information immediately from the packet, requiring no intermediate memory. The resulting data are passed to the data handler which consists of data state machines that decode data formats such as email, graphics, Hypertext Transfer Protocol (HTTP), Java, and Hypertext Markup Language (HTML).
    Type: Grant
    Filed: October 31, 1996
    Date of Patent: March 7, 2000
    Assignee: iReady Corporation
    Inventors: John Shigeto Minami, Ryo Koyama, Michael Ward Johnson, Masaru Shinohara, Thomas C. Poff, Daniel F. Burkes
  • Patent number: RE39501
    Abstract: A multiple network protocol encoder/decoder comprising a network protocol layer, data handler, O.S. State machine, and memory manager state machines implemented at a hardware gate level. Network packets are received from a physical transport level mechanism by the network protocol layer state machine which decodes network protocols such as TCP, IP, User Datagram Protocol (UDP), PPP, and Raw Socket concurrently as each byte is received. Each protocol handler parses and strips header information immediately from the packet, requiring no intermediate memory. The resulting data are passed to the data handler which consists of data state machines that decode data formats such as email, graphics, Hypertext Transfer Protocol (HTTP), Java, and Hypertext Markup Language (HTML).
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: March 6, 2007
    Assignee: NVIDIA Corporation
    Inventors: John Shigeto Minami, Ryo Koyama, Michael Ward Johnson, Masaru Shinohara, Thomas C. Poff, Daniel F. Burkes