Abstract: Sample rate converter and related methods are provided. A method may include (1) obtaining a pitch value based at least on a relationship between an input sampling rate of input samples of a first audio signal to an output sampling rate of output samples corresponding to a second audio signal; (2) automatically generating a first set of interpolated coefficient values by interpolating between a first set of coefficient values corresponding to a first filter and automatically generating a second set of interpolated coefficient values by interpolating between a second set of coefficient values corresponding to a second filter; (3) automatically generating a third set of coefficient values by interpolating between the first set of interpolated coefficient values and the second set of interpolated coefficient values using a set of fraction values related to the pitch value; and (4) filtering data corresponding to the input samples.

Abstract: MIDI-generated audio streams or other input streams of audio events are perceptually associated with specific locations in 3D space with respect to the listener. A conventional pan parameter is redefined so that it no longer specifies the relative balance between the audio being fed to two fixed speaker locations. Instead, the new MIDI pan parameter extension specifies a virtual position of an audio stream in 3D space. Preferably, the relative position of a single audio stream is set along a predefined arc in 3D space.

Abstract: A digital processing circuit for processing media data includes a data path arranged to transmit at least media data along the data path between a plurality of processing modules connected serially. The data is transmitted directly from the output of a first module to an input of a second module of the plurality by sequential clocking signals. A routing controller controls transmission of data from the first of the plurality of processing modules to any target processing module selected from the plurality of modules by providing an identification for the target processing module in a signal provided on the datapath.

Abstract: Embodiments of a signal processing system, a method, and fractionally modulated digital delay lines are generally described herein. Other embodiments may be described and claimed. In some embodiments, a fractional address is generated by adding a delay value to a fractional offset value, and input sample values are interpolated based on a fractional portion of the fractional address. A write operation may be performed to the integer portion of the fractional address for each sample period using the interpolated input sample values. Adjusted addresses may be generated when addresses are either skipped of duplicated.

Abstract: MIDI-generated audio streams or other input streams of audio events are perceptually associated with specific locations in 3D space with respect to the listener. A conventional pan parameter is redefined so that it no longer specifies the relative balance between the audio being fed to two fixed speaker locations. Instead, the new MIDI pan parameter extension specifies a virtual position of an audio stream in 3D space. Preferably, the relative position of a single audio stream is set along a predefined arc in 3D space.

Abstract: A digital processing device to process media data is provided. The device includes a plurality of processing modules to process the media data, and a media data path. The media data path communicates the media data between the processing modules, wherein the media data path is arranged in a ring configuration. In one embodiment, the media data path defines a digital audio bus that serially interconnects the plurality of processing modules. The digital audio bus may communicate digital audio data in a plurality of time-slots, each particular processing module having an associated time-slot from which data is received from the data path for processing by the particular processing module.

Abstract: Embodiments of a sample rate converter and method for sample rate conversion are generally described herein. In some embodiments, an interpolation module calculates new digital samples for insertion into a digital sample ring, a cache module provides input digital samples of a digital sample stream to the interpolation module, and a control module maintains and provides state information to the interpolation module and the cache module. Based on pitch parameters, the control module provides the interpolation module a fractional portion of an address for use in calculating the new digital samples and provides the cache module with an integer portion of the address and an address increment.

Abstract: Embodiments of a signal processing system, a method, and fractionally modulated digital delay lines are generally described herein. Other embodiments may be described and claimed. In some embodiments, a fractional address is generated by adding a delay value to a fractional offset value, and input sample values are interpolated based on a fractional portion of the fractional address. A write operation may be performed to the integer portion of the fractional address for each sample period using the interpolated input sample values. Adjusted addresses may be generated when addresses are either skipped of duplicated.

Abstract: Embodiments of a sample rate converter and method for sample rate conversion are generally described herein. In some embodiments, an interpolation module calculates new digital samples for insertion into a digital sample ring, a cache module provides input digital samples of a digital sample stream to the interpolation module, and a control module maintains and provides state information to the interpolation module and the cache module. Based on pitch parameters, the control module provides the interpolation module a fractional portion of an address for use in calculating the new digital samples and provides the cache module with an integer portion of the address and an address increment.

Abstract: A delay line circuit and method to delay digital data in a main memory is provided. The delay line circuit may comprise primary delay line cache, secondary delay line cache, and a cache controller to control communication of data between the secondary delay cache and the primary delay cache. The primary delay line cache may receive digital data to be delayed from a signal processor module, and secondary delay line cache may be connected to the primary delay line cache and the main memory to send data to and receive delayed data from the main memory. Data in the secondary delay line cache may be updated with data from the main memory or with data from the primary delay line cache. The invention extends to a machine-readable medium comprising a set of instructions for executing any of the methods described herein.

Abstract: A delay line circuit and method to delay digital data in a main memory is provided. The delay line circuit may comprise primary delay line cache, secondary delay line cache, and a cache controller to control communication of data between the secondary delay cache and the primary delay cache. The primary delay line cache may receive digital data to be delayed from a signal processor module, and secondary delay line cache may be connected to the primary delay line cache and the main memory to send data to and receive delayed data from the main memory. Data in the secondary delay line cache may be updated with data from the main memory or with data from the primary delay line cache. The invention extends to a machine-readable medium comprising a set of instructions for executing any of the methods described herein.

Abstract: A method and a digital processor circuit to process digital delays are provided. The digital processor circuit may comprise circuit memory and a processor module such as a digital signal processor (DSP), a delay line module, a filter module and a sample rate converter module. The circuit memory may comprise a digital delay line memory portion to provide a plurality of digital delay lines; and a cache memory portion to perform a pre-fetch data transfer operation from the main memory to the cache memory portion. The cache memory portion may comprise a plurality of delay caches that are updated with data samples from corresponding delay lines in the main memory. The sizes (e.g., the relative sizes) of the delay line memory portion and the cache memory portion of the circuit memory may be adjustable. The sizes may be dependent upon algorithms executed by the processor module.

Abstract: An asynchronous sample rate estimator and a method for generating a rate estimate to track an asynchronous input sampled signal is disclosed. The present invention achieves lock quickly and maintains an optimum input buffer configuration and enhanced signal fidelity by responding quickly and accurately to changes in the incoming frequency. An asynchronous sample rate estimator receives and determines a measured sample period of an asynchronous input signal. Furthermore, a reciprocal frequency error signal and a current rate estimate signal are used to generate a rate estimate for tracking the read pointer to the write pointer of a FIFO buffer, as well as a phase correction signal for centering the write pointer in the FIFO buffer. An asynchronous sample rate estimator might also include an error gain generator for providing an error gain and a lock detector for indicating whether the system has achieved a locked condition.

Abstract: An asynchronous sample rate tracker based on a phase-locked loop quickly locks to an input sample rate, even when the input sample rate equals the resident, or internal, sample rate of an asynchronous digital sample rate converter. The phase difference between the input write data and output read data is maximized to reduce data lost due to excursions in the input sample rate. In one embodiment, a binary shift register is used to generate a read pointer step size according to the derivative of the difference between a write pointer position and a read pointer position.

Abstract: A circuit for implementing digital delay lines that includes a main memory, a cache memory, and a processor. The main memory implements at least one digital delay line, as many delay lines as required by a digital signal processing (DSP) program running on the processor, up to a predetermined number. The delay lines contain data samples to be operated on, or produced by DSP program. The cache memory implements a number of delay caches that temporarily store data samples and support the delay lines. Each delay line is associated with a read cache and a write cache. A block of data samples are “pre-fetched” from a delay line in the main memory and provided to the associated read cache. The data samples in the read cache are then accessed, as needed, by the processor. Data samples generated by the DSP program are provided to the write cache. Periodically, a block of data samples is “post-written” from the write cache to its corresponding delay line in the main memory.

Abstract: Methods and circuits for the generation and application of sample rate conversion ratios using distributed jitter. In some applications, it is not possible to represent the required sample rate conversion ratio with an exact fractional binary ratio having a denominator that is a power of two. When this occurs, a fractional binary ratio is selected that approximates the required conversion ratio. The residual phase error resulting from the use of the selected fractional binary ratio is then computed and compensated for by adding a predetermined amount of “jitter.” The jitter can be distributed periodically, uniformly, or randomly over each repetition period, the period between which the input and output clock pattern repeats.