Abstract: An apparatus, system and method for determining when an LED used in traffic signal device will fail. The traffic signal apparatus comprises a housing, a solid state light disposed therein and having an array of LED generating a light output therefrom, and a circuit adapted to predict failure of the solid state light source based on a plurality of parameters at which the LED array operates. The method comprises the acts of sensing the light output generated by the LED array and sensing the ambient temperature thereby. These sensing acts are then followed by a calculating act wherein a time-average temperature value is calculated based on the intensity of both the light output and the ambient temperature. The calculating act is then followed by another calculating act wherein a time-average duty cycle value of the power source powering the LED array is determined.

Abstract: An integrated circuit (IC) comprising an integrated level shifting latch for I/O. The level shift in the IC I/O section may be clocked. In addition, a latch may be moved from the core section to the I/O section of the device, and thus the incoming clock may remain in the external voltage domain to clock the latch along with the level shift. The level shift and latch may be clocked on opposite phases of the clock. Preferably, the level shift and latch may operate differentially on the data signal. Both setup and clock-to-Q times are significantly reduced with respect to prior art devices, allowing higher speed industry specifications may be met.

Abstract: An integrated circuit (IC) comprising an integrated level shifting latch for I/O. The level shift in the IC I/O section may be clocked. In addition, a latch may be moved from the core section to the I/O section of the device, and thus the incoming clock may remain in the external voltage domain to clock the latch along with the level shift. The level shift and latch may be clocked on opposite phases of the clock. Preferably, the level shift and latch may operate differentially on the data signal. Both setup and clock-to-Q times are significantly reduced with respect to prior art devices, allowing higher speed industry specifications may be met.