Abstract: A method comprises receiving an integrated circuit (IC) design file and determining, by one or more processors, dose information from the IC design file. The method further comprises determining, by the one or more processors, a mask vector file from the IC design file, and converting, by the one or more processors, the dose information to a vector file format. Further, the method comprises outputting the dose information in the vector file format and the mask vector file to a mask writer device.

Abstract: Aspects described herein relate to mask synthesis using design guided offsets. A target shape on an image surface to be fabricated using a mask based on a design of an integrated circuit is obtained. Rays are generated emanating from respective anchor points. The anchor points are on a boundary of the target shape or a boundary of a mask shape of the mask. For each ray of the rays, a distance is defined between a first intersection of the respective ray and the boundary of the target shape and a second intersection of the respective ray and the boundary of the mask shape. An analysis is performed by one or more processors, where the analysis is configured to modify the distances based on an error between the target shape and a resulting shape simulated to be on the image surface resulting from the mask shape.

Abstract: A method comprises receiving an integrated circuit (IC) chip design, and generating, by one or more processors, a wafer image and a wafer target from the IC chip design. The method further comprises generating, by the one or more processors, sensitivity information based on a determination that the wafer image and the wafer target converge, and outputting the sensitivity information. The sensitivity information is associated with writing a mask written for the IC chip design.

Abstract: A method comprises receiving an integrated circuit (IC) chip design, and generating, by one or more processors and based on the IC chip design, dose information, a wafer image, and a wafer target. Further, the method comprises modifying, by the one or more processors, the dose information based on a comparison of the wafer image and the wafer target. Further, the method comprises outputting the modified dose information to a mask writing device.

Abstract: Aspects described herein relate to obtaining a mask pattern using a cost function gradient (CFG) generated from a Jacobian matrix generated from a perturbation look-up table (PLT). In an example method, a PLT is populated (108). Each table entry of the PLT is based on a respective perturbed intensity signal. The respective perturbed intensity signal is based on a simulated signal received at an image surface using a mask pattern having a perturbed element of the mask pattern. The mask pattern is for a design of an integrated circuit. A matrix is populated (110) using the PLT and a target intensity signal. The target intensity signal is based on a signal received at the image surface to form target features at the image surface. A CFG is defined (112) based on the matrix. An analysis is performed (114) on the mask pattern based on the CFG.

Abstract: An example is a method. An electronic representation of a design of an integrated circuit to be manufactured on a semiconductor die is obtained. The design of the integrated circuit includes layers. The electronic representation includes initial polygons. Polygon topological skeletons of the initial polygons of the target layer are generated. A space topological skeleton in a space between the polygon topological skeletons is generated. A connected network comprising network edges is generated. Each network edge is connected between a respective polygon topological skeleton and the space topological skeleton. A transformation of the polygon topological skeletons is performed, by one or more processors, based on the network edges, a spacing specification for a spacing between polygons, and respective specified widths associated with the initial polygons by perturbing the polygon topological skeletons.

Abstract: A method comprises receiving an integrated circuit (IC) design file and determining, by one or more processors, dose information from the IC design file. The method further comprises determining, by the one or more processors, a mask vector file from the IC design file, and converting, by the one or more processors, the dose information to a vector file format. Further, the method comprises outputting the dose information in the vector file format and the mask vector file to a mask writer device.

Abstract: A method comprises receiving an integrated circuit (IC) chip design, and generating, by one or more processors, a wafer image and a wafer target from the IC chip design. The method further comprises generating, by the one or more processors, sensitivity information based on a determination that the wafer image and the wafer target converge, and outputting the sensitivity information. The sensitivity information is associated with writing a mask written for the IC chip design.

Abstract: A method comprises receiving an integrated circuit (IC) chip design, and generating, by one or more processors and based on the IC chip design, dose information, a wafer image, and a wafer target. Further, the method comprises modifying, by the one or more processors, the dose information based on a comparison of the wafer image and the wafer target. Further, the method comprises outputting the modified dose information to a mask writing device.

Abstract: Aspects described herein relate to mask synthesis using design guided offsets. A target shape on an image surface to be fabricated using a mask based on a design of an integrated circuit is obtained. Rays are generated emanating from respective anchor points. The anchor points are on a boundary of the target shape or a boundary of a mask shape of the mask. For each ray of the rays, a distance is defined between a first intersection of the respective ray and the boundary of the target shape and a second intersection of the respective ray and the boundary of the mask shape. An analysis is performed by one or more processors, where the analysis is configured to modify the distances based on an error between the target shape and a resulting shape simulated to be on the image surface resulting from the mask shape.

Abstract: Aspects described herein relate to obtaining a mask pattern using a cost function gradient (CFG) generated from a Jacobian matrix generated from a perturbation look-up table (PLT). In an example method, a PLT is populated (108). Each table entry of the PLT is based on a respective perturbed intensity signal. The respective perturbed intensity signal is based on a simulated signal received at an image surface using a mask pattern having a perturbed element of the mask pattern. The mask pattern is for a design of an integrated circuit. A matrix is populated (110) using the PLT and a target intensity signal. The target intensity signal is based on a signal received at the image surface to form target features at the image surface. A CFG is defined (112) based on the matrix. An analysis is performed (114) on the mask pattern based on the CFG.

Abstract: Aspects described herein relate to obtaining a mask pattern using a cost function gradient (CFG) generated from a Jacobian matrix generated from a perturbation look-up table (PLT). In an example method, a PLT is populated (108). Each table entry of the PLT is based on a respective perturbed intensity signal. The respective perturbed intensity signal is based on a simulated signal received at an image surface using a mask pattern having a perturbed element of the mask pattern. The mask pattern is for a design of an integrated circuit. A matrix is populated (110) using the PLT and a target intensity signal. The target intensity signal is based on a signal received at the image surface to form target features at the image surface. A CFG is defined (112) based on the matrix. An analysis is performed (114) on the mask pattern based on the CFG.

Abstract: An example is a method. An electronic representation of a design of an integrated circuit to be manufactured on a semiconductor die is obtained. The design of the integrated circuit includes layers. The electronic representation includes initial polygons. Polygon topological skeletons of the initial polygons of the target layer are generated. A space topological skeleton in a space between the polygon topological skeletons is generated. A connected network comprising network edges is generated. Each network edge is connected between a respective polygon topological skeleton and the space topological skeleton. A transformation of the polygon topological skeletons is performed, by one or more processors, based on the network edges, a spacing specification for a spacing between polygons, and respective specified widths associated with the initial polygons by perturbing the polygon topological skeletons.

Abstract: A microcalorimeter for radiation detection that uses superconducting kinetic inductance resonators as the thermometers. The detector is frequency-multiplexed which enables detector systems with a large number of pixels.

Abstract: A microcalorimeter for radiation detection that uses superconducting kinetic inductance resonators as the thermometers. The detector is frequency-multiplexed which enables detector systems with a large number of pixels.

Abstract: A particle vibration damper includes a container which locates a plurality of steel particles. A copper winding is provided around the container to induce a magnetic field therein to increase the inter-particle pressure. By adjusting the voltage across the winding the amplitude of peak damping ability can be varied to match the vibration amplitude being damped.