Patents by Inventor Thomas Cecil
Thomas Cecil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11932805Abstract: A bulk dry cement may comprise a cement; a solid particle; and a liquid resin accelerator, wherein the liquid resin accelerator is disposed on a surface of the solid particle.Type: GrantFiled: September 24, 2021Date of Patent: March 19, 2024Assignee: Halliburton Energy Services, Inc.Inventors: Paul Joseph Jones, William Cecil Pearl, Jr., Samuel Jason Lewis, Thomas Jason Pisklak
-
Patent number: 11822232Abstract: A method comprises receiving an integrated circuit (IC) design file and determining, by one or more processors, dose information from the IC design file. The method further comprises determining, by the one or more processors, a mask vector file from the IC design file, and converting, by the one or more processors, the dose information to a vector file format. Further, the method comprises outputting the dose information in the vector file format and the mask vector file to a mask writer device.Type: GrantFiled: July 23, 2021Date of Patent: November 21, 2023Assignee: Synopsys, Inc.Inventor: Thomas Cecil
-
Patent number: 11720015Abstract: Aspects described herein relate to mask synthesis using design guided offsets. A target shape on an image surface to be fabricated using a mask based on a design of an integrated circuit is obtained. Rays are generated emanating from respective anchor points. The anchor points are on a boundary of the target shape or a boundary of a mask shape of the mask. For each ray of the rays, a distance is defined between a first intersection of the respective ray and the boundary of the target shape and a second intersection of the respective ray and the boundary of the mask shape. An analysis is performed by one or more processors, where the analysis is configured to modify the distances based on an error between the target shape and a resulting shape simulated to be on the image surface resulting from the mask shape.Type: GrantFiled: June 25, 2021Date of Patent: August 8, 2023Assignee: Synopsys, Inc.Inventors: Thomas Cecil, Kevin Hooker
-
Patent number: 11657207Abstract: A method comprises receiving an integrated circuit (IC) chip design, and generating, by one or more processors, a wafer image and a wafer target from the IC chip design. The method further comprises generating, by the one or more processors, sensitivity information based on a determination that the wafer image and the wafer target converge, and outputting the sensitivity information. The sensitivity information is associated with writing a mask written for the IC chip design.Type: GrantFiled: July 16, 2021Date of Patent: May 23, 2023Assignee: Synopsys, Inc.Inventor: Thomas Cecil
-
Patent number: 11651135Abstract: A method comprises receiving an integrated circuit (IC) chip design, and generating, by one or more processors and based on the IC chip design, dose information, a wafer image, and a wafer target. Further, the method comprises modifying, by the one or more processors, the dose information based on a comparison of the wafer image and the wafer target. Further, the method comprises outputting the modified dose information to a mask writing device.Type: GrantFiled: July 23, 2021Date of Patent: May 16, 2023Assignee: Synopsys, Inc.Inventor: Thomas Cecil
-
Patent number: 11644747Abstract: Aspects described herein relate to obtaining a mask pattern using a cost function gradient (CFG) generated from a Jacobian matrix generated from a perturbation look-up table (PLT). In an example method, a PLT is populated (108). Each table entry of the PLT is based on a respective perturbed intensity signal. The respective perturbed intensity signal is based on a simulated signal received at an image surface using a mask pattern having a perturbed element of the mask pattern. The mask pattern is for a design of an integrated circuit. A matrix is populated (110) using the PLT and a target intensity signal. The target intensity signal is based on a signal received at the image surface to form target features at the image surface. A CFG is defined (112) based on the matrix. An analysis is performed (114) on the mask pattern based on the CFG.Type: GrantFiled: June 4, 2021Date of Patent: May 9, 2023Assignee: Synopsys, Inc.Inventor: Thomas Cecil
-
Patent number: 11449659Abstract: An example is a method. An electronic representation of a design of an integrated circuit to be manufactured on a semiconductor die is obtained. The design of the integrated circuit includes layers. The electronic representation includes initial polygons. Polygon topological skeletons of the initial polygons of the target layer are generated. A space topological skeleton in a space between the polygon topological skeletons is generated. A connected network comprising network edges is generated. Each network edge is connected between a respective polygon topological skeleton and the space topological skeleton. A transformation of the polygon topological skeletons is performed, by one or more processors, based on the network edges, a spacing specification for a spacing between polygons, and respective specified widths associated with the initial polygons by perturbing the polygon topological skeletons.Type: GrantFiled: May 6, 2020Date of Patent: September 20, 2022Assignee: Synopsys, Inc.Inventor: Thomas Cecil
-
Publication number: 20220035242Abstract: A method comprises receiving an integrated circuit (IC) chip design, and generating, by one or more processors and based on the IC chip design, dose information, a wafer image, and a wafer target. Further, the method comprises modifying, by the one or more processors, the dose information based on a comparison of the wafer image and the wafer target. Further, the method comprises outputting the modified dose information to a mask writing device.Type: ApplicationFiled: July 23, 2021Publication date: February 3, 2022Inventor: Thomas CECIL
-
Publication number: 20220035241Abstract: A method comprises receiving an integrated circuit (IC) design file and determining, by one or more processors, dose information from the IC design file. The method further comprises determining, by the one or more processors, a mask vector file from the IC design file, and converting, by the one or more processors, the dose information to a vector file format. Further, the method comprises outputting the dose information in the vector file format and the mask vector file to a mask writer device.Type: ApplicationFiled: July 23, 2021Publication date: February 3, 2022Inventor: Thomas CECIL
-
Publication number: 20220035240Abstract: A method comprises receiving an integrated circuit (IC) chip design, and generating, by one or more processors, a wafer image and a wafer target from the IC chip design. The method further comprises generating, by the one or more processors, sensitivity information based on a determination that the wafer image and the wafer target converge, and outputting the sensitivity information. The sensitivity information is associated with writing a mask written for the IC chip design.Type: ApplicationFiled: July 16, 2021Publication date: February 3, 2022Inventor: Thomas CECIL
-
Publication number: 20210405522Abstract: Aspects described herein relate to mask synthesis using design guided offsets. A target shape on an image surface to be fabricated using a mask based on a design of an integrated circuit is obtained. Rays are generated emanating from respective anchor points. The anchor points are on a boundary of the target shape or a boundary of a mask shape of the mask. For each ray of the rays, a distance is defined between a first intersection of the respective ray and the boundary of the target shape and a second intersection of the respective ray and the boundary of the mask shape. An analysis is performed by one or more processors, where the analysis is configured to modify the distances based on an error between the target shape and a resulting shape simulated to be on the image surface resulting from the mask shape.Type: ApplicationFiled: June 25, 2021Publication date: December 30, 2021Inventors: Thomas CECIL, Kevin HOOKER
-
Publication number: 20210294207Abstract: Aspects described herein relate to obtaining a mask pattern using a cost function gradient (CFG) generated from a Jacobian matrix generated from a perturbation look-up table (PLT). In an example method, a PLT is populated (108). Each table entry of the PLT is based on a respective perturbed intensity signal. The respective perturbed intensity signal is based on a simulated signal received at an image surface using a mask pattern having a perturbed element of the mask pattern. The mask pattern is for a design of an integrated circuit. A matrix is populated (110) using the PLT and a target intensity signal. The target intensity signal is based on a signal received at the image surface to form target features at the image surface. A CFG is defined (112) based on the matrix. An analysis is performed (114) on the mask pattern based on the CFG.Type: ApplicationFiled: June 4, 2021Publication date: September 23, 2021Inventor: Thomas CECIL
-
Patent number: 11061321Abstract: Aspects described herein relate to obtaining a mask pattern using a cost function gradient (CFG) generated from a Jacobian matrix generated from a perturbation look-up table (PLT). In an example method, a PLT is populated (108). Each table entry of the PLT is based on a respective perturbed intensity signal. The respective perturbed intensity signal is based on a simulated signal received at an image surface using a mask pattern having a perturbed element of the mask pattern. The mask pattern is for a design of an integrated circuit. A matrix is populated (110) using the PLT and a target intensity signal. The target intensity signal is based on a signal received at the image surface to form target features at the image surface. A CFG is defined (112) based on the matrix. An analysis is performed (114) on the mask pattern based on the CFG.Type: GrantFiled: June 12, 2020Date of Patent: July 13, 2021Assignee: Synopsys, Inc.Inventor: Thomas Cecil
-
Publication number: 20200379344Abstract: An example is a method. An electronic representation of a design of an integrated circuit to be manufactured on a semiconductor die is obtained. The design of the integrated circuit includes layers. The electronic representation includes initial polygons. Polygon topological skeletons of the initial polygons of the target layer are generated. A space topological skeleton in a space between the polygon topological skeletons is generated. A connected network comprising network edges is generated. Each network edge is connected between a respective polygon topological skeleton and the space topological skeleton. A transformation of the polygon topological skeletons is performed, by one or more processors, based on the network edges, a spacing specification for a spacing between polygons, and respective specified widths associated with the initial polygons by perturbing the polygon topological skeletons.Type: ApplicationFiled: May 6, 2020Publication date: December 3, 2020Inventor: Thomas CECIL
-
Patent number: 9523777Abstract: A microcalorimeter for radiation detection that uses superconducting kinetic inductance resonators as the thermometers. The detector is frequency-multiplexed which enables detector systems with a large number of pixels.Type: GrantFiled: April 10, 2014Date of Patent: December 20, 2016Assignee: UChicago Argonne, LLCInventors: Thomas Cecil, Lisa Gades, Antonio Miceli, Orlando Quaranta
-
Publication number: 20150293236Abstract: A microcalorimeter for radiation detection that uses superconducting kinetic inductance resonators as the thermometers. The detector is frequency-multiplexed which enables detector systems with a large number of pixels.Type: ApplicationFiled: April 10, 2014Publication date: October 15, 2015Applicant: UChicago Argonne, LLCInventors: Thomas Cecil, Lisa Gades, Antonio Miceli, Orlando Quaranta
-
Patent number: 8127419Abstract: An environmentally responsible system and method of reusing discarded guardrail materials to provide affordable, high-strength barriers and fencing. Discarded guardrails, guardrail posts, and guardrail blockouts are resized and reconfigured to provide barriers for use in alternative applications, such as agrifencing, where the high-strength, durability, and low cost of these formerly DOT-approved guardrail materials provide superior performance to wood and thin metal barriers. The invention also greatly increases the return on investment of state DOTs by providing an aftermarket for used guardrail materials, thereby allowing state DOTs to recover much of the initial costs, which can then be used to offset future costs in order facilitate more highway improvement projects.Type: GrantFiled: March 11, 2009Date of Patent: March 6, 2012Inventors: Thomas Cecil Calton, Terry Francis Jordan
-
Patent number: 7983490Abstract: A system and method for classifying input patterns into two classes, a class-of-interest and a class-other, utilizing a method for estimating an optimal Bayes decision boundary for discriminating between the class-of-interest and class-other, when training samples or otherwise, are provided a priori only for the class-of-interest thus eliminates the requirement for any a priori knowledge of the other classes in the data set to be classified, while exploiting the robust and powerful discriminating capability provided by fully supervised Bayes classification approaches. The system and method may be used in applications where class definitions, through training samples or otherwise, are provided a priori only for the classes-of-interest. The distribution of the other-class may be unknown or may have changed. Often one is only interested in one class or a small number of classes.Type: GrantFiled: December 20, 2007Date of Patent: July 19, 2011Inventor: Thomas Cecil Minter
-
Patent number: 7979363Abstract: A system and method for estimating the a priori probability of a class-of-interest in an input-data-set and a system and method for evaluating the performance of the adaptive Bayes classifier in classifying unlabeled samples from an input-put-data-set. The adaptive Bayes classifier provides a capability to classify data into two classes, a class-of-interest or a class-other, with minimum classification error in an environment where a priori knowledge, through training samples or otherwise, is only available for a single class, the class-of-interest. This invention provides a method and system for estimating the a priori probability of the class-of-interest in the data set to be classified and evaluating adaptive Bayes classifier performance in classifying data into two classes, a class-of-interest and a class-other, using only labeled training samples, or otherwise, from the class-of-interest and unlabeled samples from the data set to be classified.Type: GrantFiled: March 6, 2008Date of Patent: July 12, 2011Inventor: Thomas Cecil Minter
-
Patent number: 7974475Abstract: This invention relates generally to a system and method for correlating two images for the purpose of identifying a target in an image where templates are provided a priori only for the target. Information on other objects in the image being searched may be unavailable or difficult to obtain. This invention treats the design of target matching-templates and target matched-filters for image correlation as a statistical pattern recognition problem. By minimizing a suitable criterion, a target matching-template or a target matched-filter is estimated which approximates the optimal Bayes discriminant function in a least-squares sense. Both Bayesian image correlation methods identify the target with minimum probability of error while requiring no prior knowledge of other objects in the image being searched. The system and method is adaptive in that it can be re-optimizing (adapted) to recognize the target in a new search image using only information from the new image.Type: GrantFiled: August 20, 2009Date of Patent: July 5, 2011Inventor: Thomas Cecil Minter