Patents by Inventor Thomas Champseix

Thomas Champseix has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hardware synchronization barrier between processing units
    Patent number: 9766951
    Abstract: A method for synchronizing multiple processing units, comprises the steps of configuring a synchronization register in a target processing unit so that its content is overwritten only by bits that are set in words written in the synchronization register; assigning a distinct bit position of the synchronization register to each processing unit; and executing a program thread in each processing unit. When the program thread of a current processing unit reaches a synchronization point, the method comprises writing in the synchronization register of the target processing unit a word in which the bit position assigned to the current processing unit is set, and suspending the program thread. When all the bits assigned to the processing units are set in the synchronization register, the suspended program threads are resumed.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: September 19, 2017
    Assignee: KALRAY
    Inventors: Thomas Champseix, Benoît Dupont De Dinechin, Pierre Guironnet De Massas
  • Stream management in an on-chip network
    Patent number: 9565122
    Abstract: A credit-based data flow control method between a consumer device and a producer device. The method includes the steps of decrementing a credit counter for each transmission of a sequence of data by the producer device, arresting data transmission when the credit counter reaches zero, sending a credit each time the consumer device has consumed a data sequence and incrementing the credit counter upon receipt of each credit.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: February 7, 2017
    Assignee: KALRAY
    Inventors: Michel Harrand, Yves Durand, Patrice Couvert, Thomas Champseix, Benoît Dupont De Dinechin
  • HARDWARE SYNCHRONIZATION BARRIER BETWEEN PROCESSING UNITS
    Publication number: 20150339173
    Abstract: A method for synchronizing multiple processing units, comprises the steps of configuring a synchronization register in a target processing unit so that its content is overwritten only by bits that are set in words written in the synchronization register; assigning a distinct bit position of the synchronization register to each processing unit; and executing a program thread in each processing unit. When the program thread of a current processing unit reaches a synchronization point, the method comprises writing in the synchronization register of the target processing unit a word in which the bit position assigned to the current processing unit is set, and suspending the program thread. When all the bits assigned to the processing units are set in the synchronization register, the suspended program threads are resumed.
    Type: Application
    Filed: May 26, 2015
    Publication date: November 26, 2015
    Inventors: Thomas CHAMPSEIX, Benoît DUPONT DE DINECHIN, Pierre GUIRONNET DE MASSAS
  • STREAM MANAGEMENT IN AN ON-CHIP NETWORK
    Publication number: 20140301205
    Abstract: A credit-based data flow control method between a consumer device and a producer device. The method includes the steps of decrementing a credit counter for each transmission of a sequence of data by the producer device, arresting data transmission when the credit counter reaches zero, sending a credit each time the consumer device has consumed a data sequence and incrementing the credit counter upon receipt of each credit.
    Type: Application
    Filed: October 9, 2012
    Publication date: October 9, 2014
    Inventors: Michel Harrand, Yves Durand, Patrice Couvert, Thomas Champseix, Benoît Dupont De Dinechin