Abstract: A method, system and computer program product are provided for implementing routing first for rapid prototyping and improved wiring of heterogeneous hierarchical integrated circuit chips. Placement for each of a plurality of random logic macros (RLMs) is identified. Predefined wiring shapes are created for each of the identified RLMs. Full chip wire routing is defined responsive to the created predefined wiring shapes for each of the identified RLMs.

Abstract: A method, system and computer program product are provided for implementing routing first for rapid prototyping and improved wiring of heterogeneous hierarchical integrated circuit chips. Placement for each of a plurality of random logic macros (RLMs) is identified. Predefined wiring shapes are created for each of the identified RLMs. Full chip wire routing is defined responsive to the created predefined wiring shapes for each of the identified RLMs.

Abstract: A method of modifying an integrated circuit design. A noise threshold is determined. A threshold, noisy wire length for a particular integrated circuit design is selected. An integrated circuit design is examined for problem networks or wires and all branches that cumulatively equal or exceed the designated threshold noisy wire length. Once the problem networks are identified, the driver circuits driving the problem networks are temporarily replaced with driver circuits with lesser driving capacity. The integrated circuit design is then tested and any new timing failures are identified. Networks that include new timing failures are isolated with symmetric and/or asymmetric wire configurations. This method of modifying an integrated circuit design is non-intrusive to existing neighboring wires, and thus the timing in existing wires is preserved.

Abstract: A method is shown which replaces single vias with redundant vias on candidate signals on a semiconductor integrated circuit chip. Where limited space prevents such replacement on more than one signal wire, the method assigns priority to the via through which more current must flow to charge or discharge capacitance. This prioritization reduces the magnitude of delay anomalies arising from vias containing process related resistance defects.

Abstract: A method is shown which replaces single vias with redundant vias on candidate signals on a semiconductor integrated circuit chip. Where limited space prevents such replacement on more than one signal wire, the method assigns priority to the via through which more current must flow to charge or discharge capacitance. This prioritization reduces the magnitude of delay anomalies arising from vias containing process related resistance defects.

Abstract: A method is shown which replaces single vias with redundant vias on candidate signals on a semiconductor integrated circuit chip. Where limited space prevents such replacement on more than one signal wire, the method assigns priority to the via through which more current must flow to charge or discharge capacitance. This prioritization reduces the magnitude of delay anomalies arising from vias containing process related resistance defects.

Abstract: A method is shown which replaces single vias with redundant vias on candidate signals on a semiconductor integrated circuit chip. Where limited space prevents such replacement on more than one signal wire, the method assigns priority to the via through which more current must flow to charge or discharge capacitance. This prioritization reduces the magnitude of delay anomalies arising from vias containing process related resistance defects.

Abstract: A method is shown which replaces single vias with redundant vias on candidate signals on a semiconductor integrated circuit chip. Where limited space prevents such replacement on more than one signal wire, the method assigns priority to the via through which more current must flow to charge or discharge capacitance. This prioritization reduces the magnitude of delay anomalies arising from vias containing process related resistance defects.

Abstract: A method is shown which replaces single vias with redundant vias on candidate signals on a semiconductor integrated circuit chip. Where limited space prevents such replacement on more than one signal wire, the method assigns priority to the via through which more current must flow to charge or discharge capacitance. This prioritization reduces the magnitude of delay anomalies arising from vias containing process related resistance defects.

Abstract: An automated method for designing a signal distribution network in an integrated circuit confines the circuits relating to a particular signal, such as a clock signal, to multiple areas equally distributed over the integrated circuit. Each of the multiple areas have tightly-coupled logic connected to a root driver circuit in which the root driver circuit is connected to the signal input. Within the areas of tightly-coupled logic, user-defined placement circuits or groups such as a programmable clock delay having gates, delays, and splitters are connected to the root driver circuit in accordance with wire capacitance targets and input pin load balancing among all the multiple areas. The input pin load balancing and the wire capacitance targets of the user-defined placement groups connected to the root driver circuit in one of the multiple areas matches the input pin load balancing and the wire capacitance targets of other groups connected to other root driver circuits in other multiple areas.