Patents by Inventor Thomas Christian Neidhart

Thomas Christian Neidhart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230207451
    Abstract: A multi-voltage domain device includes a semiconductor layer including a first main surface, a second main surface arranged opposite to the first main surface, a first region including first circuitry that operates in a first voltage domain, a second region including second circuitry that operates in a second voltage domain different than the first voltage domain, and an isolation region that electrically isolates the first region from the second region in a lateral direction that extends parallel to the first and the second main surfaces. The isolation region includes at least one deep trench isolation barrier, each of which extends vertically from the first main surface to the second main surface. The multi-voltage domain device further includes at least one first capacitor configured to generate an electric field laterally across the isolation region between the first region and the second region.
    Type: Application
    Filed: February 21, 2023
    Publication date: June 29, 2023
    Inventors: Lars MUELLER-MESKAMP, Berthold ASTEGHER, Hermann GRUBER, Thomas Christian NEIDHART
  • Patent number: 11664307
    Abstract: A multi-voltage domain device includes a semiconductor layer including a first main surface, a second main surface arranged opposite to the first main surface, a first region including first circuity that operates in a first voltage domain, a second region including second circuity that operates in a second voltage domain different than the first voltage domain, and an isolation region that electrically isolates the first region from the second region in a lateral direction that extends parallel to the first and the second main surfaces. The isolation region includes at least one deep trench isolation barrier, each of which extends vertically from the first main surface to the second main surface. The multi-voltage domain device further includes at least one first capacitor configured to generate an electric field laterally across the isolation region between the first region and the second region.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: May 30, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Lars Mueller-Meskamp, Berthold Astegher, Hermann Gruber, Thomas Christian Neidhart
  • Publication number: 20220059453
    Abstract: A multi-voltage domain device includes a semiconductor layer including a first main surface, a second main surface arranged opposite to the first main surface, a first region including first circuity that operates in a first voltage domain, a second region including second circuity that operates in a second voltage domain different than the first voltage domain, and an isolation region that electrically isolates the first region from the second region in a lateral direction that extends parallel to the first and the second main surfaces. The isolation region includes at least one deep trench isolation barrier, each of which extends vertically from the first main surface to the second main surface. The multi-voltage domain device further includes at least one first capacitor configured to generate an electric field laterally across the isolation region between the first region and the second region.
    Type: Application
    Filed: November 3, 2021
    Publication date: February 24, 2022
    Applicant: Infineon Technologies Austria AG
    Inventors: Lars MUELLER-MESKAMP, Berthold ASTEGHER, Hermann GRUBER, Thomas Christian NEIDHART
  • Patent number: 11183452
    Abstract: A multi-voltage domain device includes a semiconductor layer including a first main surface, a second main surface arranged opposite to the first main surface, a first region including first circuitry that operates in a first voltage domain, a second region including second circuitry that operates in a second voltage domain different than the first voltage domain, and an isolation region that electrically isolates the first region from the second region in a lateral direction that extends parallel to the first and the second main surfaces. The isolation region includes at least one deep trench isolation barrier, each of which extends vertically from the first main surface to the second main surface. The multi-voltage domain device further includes at least one first capacitor configured to generate an electric field laterally across the isolation region between the first region and the second region.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: November 23, 2021
    Inventors: Lars Mueller-Meskamp, Berthold Astegher, Hermann Gruber, Thomas Christian Neidhart
  • Patent number: 11038028
    Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having opposing first and second main surfaces and first and second dopants. A covalent atomic radius of a material of the substrate is i) larger than a covalent atomic radius of the first dopant and smaller than that of the second dopant, or ii) smaller than the covalent atomic radius of the first dopant and larger than that of the second dopant. A vertical extension of the first dopant into the substrate from the first main surface ends at a bottom of a substrate portion at a first vertical distance to the first main surface. The method further includes forming a semiconductor layer on the first main surface, forming semiconductor device elements in the semiconductor layer, and reducing a thickness of the substrate by removing material from the second main surface at least up to the substrate portion.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: June 15, 2021
    Assignee: Infineon Technologies AG
    Inventors: Ingo Muri, Johannes Konrad Baumgartl, Oliver Hellmund, Jacob Tillmann Ludwig, Iris Moder, Thomas Christian Neidhart, Gerhard Schmidt, Hans-Joachim Schulze
  • Patent number: 11011409
    Abstract: A semiconductor device includes a first epitaxial layer, a second epitaxial layer disposed below the first epitaxial layer, a conductive layer disposed below and directly contacting the second epitaxial layer, and a plurality of spacers disposed between the second epitaxial layer and the conductive layer. The conductive layer includes a metal. The plurality of spacers include a bulk semiconductor material.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: May 18, 2021
    Assignee: Infineon Technologies AG
    Inventors: Oliver Hellmund, Ingo Muri, Johannes Baumgartl, Iris Moder, Thomas Christian Neidhart, Hans-Joachim Schulze
  • Publication number: 20200098617
    Abstract: A semiconductor device includes a first epitaxial layer, a second epitaxial layer disposed below the first epitaxial layer, a conductive layer disposed below and directly contacting the second epitaxial layer, and a plurality of spacers disposed between the second epitaxial layer and the conductive layer. The conductive layer includes a metal. The plurality of spacers include a bulk semiconductor material.
    Type: Application
    Filed: November 26, 2019
    Publication date: March 26, 2020
    Inventors: Oliver Hellmund, Ingo Muri, Johannes Baumgartl, Iris Moder, Thomas Christian Neidhart, Hans-Joachim Schulze
  • Patent number: 10535553
    Abstract: A semiconductor device includes a trench extending through a semiconductor substrate and an epitaxial layer disposed over a first side of the semiconductor substrate. The epitaxial layer partially fills a portion of the trench. The semiconductor device further includes a back side metal layer disposed over a second side of the semiconductor substrate. The back side metal layer extends into the trench and fills the remaining portion of the trench. The epitaxial layer partially filling the trench contacts the back side metal layer filling the remaining portion within the trench.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: January 14, 2020
    Assignee: Infineon Technologies AG
    Inventors: Oliver Hellmund, Ingo Muri, Johannes Baumgartl, Iris Moder, Thomas Christian Neidhart, Hans-Joachim Schulze
  • Publication number: 20190348506
    Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having opposing first and second main surfaces and first and second dopants. A covalent atomic radius of a material of the substrate is i) larger than a covalent atomic radius of the first dopant and smaller than that of the second dopant, or ii) smaller than the covalent atomic radius of the first dopant and larger than that of the second dopant. A vertical extension of the first dopant into the substrate from the first main surface ends at a bottom of a substrate portion at a first vertical distance to the first main surface. The method further includes forming a semiconductor layer on the first main surface, forming semiconductor device elements in the semiconductor layer, and reducing a thickness of the substrate by removing material from the second main surface at least up to the substrate portion.
    Type: Application
    Filed: May 8, 2019
    Publication date: November 14, 2019
    Inventors: Ingo Muri, Johannes Konrad Baumgartl, Oliver Hellmund, Jacob Tillmann Ludwig, Iris Moder, Thomas Christian Neidhart, Gerhard Schmidt, Hans-Joachim Schulze
  • Patent number: 10325804
    Abstract: In accordance with an embodiment of the present invention, a method of fabricating a semiconductor device includes forming openings partially filled with a sacrificial material, where the openings extend into a semiconductor substrate from a first side. A void region is formed in a central region of the openings. An epitaxial layer is formed over the first side of the semiconductor substrate and the openings, where the epitaxial layer covers the void region. From a second side of the semiconductor substrate opposite to the first side, the semiconductor substrate is thinned to expose the sacrificial material. The sacrificial material in the openings is removed and the epitaxial layer is exposed. A conductive material is deposited on the exposed surface of the epitaxial layer.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: June 18, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Oliver Hellmund, Johannes Baumgartl, Iris Moder, Ingo Muri, Thomas Christian Neidhart, Hans-Joachim Schulze
  • Publication number: 20180233399
    Abstract: A semiconductor device includes a trench extending through a semiconductor substrate and an epitaxial layer disposed over a first side of the semiconductor substrate. The epitaxial layer partially fills a portion of the trench. The semiconductor device further includes a back side metal layer disposed over a second side of the semiconductor substrate. The back side metal layer extends into the trench and fills the remaining portion of the trench. The epitaxial layer partially filling the trench contacts the back side metal layer filling the remaining portion within the trench.
    Type: Application
    Filed: April 12, 2018
    Publication date: August 16, 2018
    Inventors: Oliver Hellmund, Ingo Muri, Johannes Baumgartl, Iris Moder, Thomas Christian Neidhart, Hans-Joachim Schulze
  • Publication number: 20180144974
    Abstract: In accordance with an embodiment of the present invention, a method of fabricating a semiconductor device includes forming openings partially filled with a sacrificial material, where the openings extend into a semiconductor substrate from a first side. A void region is formed in a central region of the openings. An epitaxial layer is formed over the first side of the semiconductor substrate and the openings, where the epitaxial layer covers the void region. From a second side of the semiconductor substrate opposite to the first side, the semiconductor substrate is thinned to expose the sacrificial material. The sacrificial material in the openings is removed and the epitaxial layer is exposed. A conductive material is deposited on the exposed surface of the epitaxial layer.
    Type: Application
    Filed: December 29, 2017
    Publication date: May 24, 2018
    Inventors: Oliver Hellmund, Johannes Baumgartl, Iris Moder, Ingo Muri, Thomas Christian Neidhart, Hans-Joachim Schulze
  • Patent number: 9960076
    Abstract: A method of fabricating a semiconductor device includes forming trenches filled with a sacrificial material. The trenches extend into a semiconductor substrate from a first side. An epitaxial layer is formed over the first side of the semiconductor substrate and the trenches. From a second side of the semiconductor substrate opposite to the first side, the sacrificial material in the trenches is removed. The trenches are filled with a conductive material.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: May 1, 2018
    Assignee: Infineon Technologies AG
    Inventors: Oliver Hellmund, Ingo Muri, Johannes Baumgartl, Iris Moder, Thomas Christian Neidhart, Hans-Joachim Schulze
  • Publication number: 20180082882
    Abstract: A wafer chuck configured to support a wafer during a wafer test procedure comprises a contact portion for supporting the wafer while being in contact with the wafer. The contact portion is made of a conductive material, the conductive material having a melting point larger than 1500° C.
    Type: Application
    Filed: September 11, 2017
    Publication date: March 22, 2018
    Inventors: Rudolf Zelsacher, Peter Irsigler, Thomas Christian Neidhart
  • Publication number: 20180040504
    Abstract: A method of fabricating a semiconductor device includes forming trenches filled with a sacrificial material. The trenches extend into a semiconductor substrate from a first side. An epitaxial layer is formed over the first side of the semiconductor substrate and the trenches. From a second side of the semiconductor substrate opposite to the first side, the sacrificial material in the trenches is removed. The trenches are filled with a conductive material.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 8, 2018
    Inventors: Oliver Hellmund, Ingo Muri, Johannes Baumgartl, Iris Moder, Thomas Christian Neidhart, Hans-Joachim Schulze