Patents by Inventor Thomas Christian Neidhart
Thomas Christian Neidhart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230207451Abstract: A multi-voltage domain device includes a semiconductor layer including a first main surface, a second main surface arranged opposite to the first main surface, a first region including first circuitry that operates in a first voltage domain, a second region including second circuitry that operates in a second voltage domain different than the first voltage domain, and an isolation region that electrically isolates the first region from the second region in a lateral direction that extends parallel to the first and the second main surfaces. The isolation region includes at least one deep trench isolation barrier, each of which extends vertically from the first main surface to the second main surface. The multi-voltage domain device further includes at least one first capacitor configured to generate an electric field laterally across the isolation region between the first region and the second region.Type: ApplicationFiled: February 21, 2023Publication date: June 29, 2023Inventors: Lars MUELLER-MESKAMP, Berthold ASTEGHER, Hermann GRUBER, Thomas Christian NEIDHART
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Patent number: 11664307Abstract: A multi-voltage domain device includes a semiconductor layer including a first main surface, a second main surface arranged opposite to the first main surface, a first region including first circuity that operates in a first voltage domain, a second region including second circuity that operates in a second voltage domain different than the first voltage domain, and an isolation region that electrically isolates the first region from the second region in a lateral direction that extends parallel to the first and the second main surfaces. The isolation region includes at least one deep trench isolation barrier, each of which extends vertically from the first main surface to the second main surface. The multi-voltage domain device further includes at least one first capacitor configured to generate an electric field laterally across the isolation region between the first region and the second region.Type: GrantFiled: November 3, 2021Date of Patent: May 30, 2023Assignee: Infineon Technologies Austria AGInventors: Lars Mueller-Meskamp, Berthold Astegher, Hermann Gruber, Thomas Christian Neidhart
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Publication number: 20220059453Abstract: A multi-voltage domain device includes a semiconductor layer including a first main surface, a second main surface arranged opposite to the first main surface, a first region including first circuity that operates in a first voltage domain, a second region including second circuity that operates in a second voltage domain different than the first voltage domain, and an isolation region that electrically isolates the first region from the second region in a lateral direction that extends parallel to the first and the second main surfaces. The isolation region includes at least one deep trench isolation barrier, each of which extends vertically from the first main surface to the second main surface. The multi-voltage domain device further includes at least one first capacitor configured to generate an electric field laterally across the isolation region between the first region and the second region.Type: ApplicationFiled: November 3, 2021Publication date: February 24, 2022Applicant: Infineon Technologies Austria AGInventors: Lars MUELLER-MESKAMP, Berthold ASTEGHER, Hermann GRUBER, Thomas Christian NEIDHART
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Patent number: 11183452Abstract: A multi-voltage domain device includes a semiconductor layer including a first main surface, a second main surface arranged opposite to the first main surface, a first region including first circuitry that operates in a first voltage domain, a second region including second circuitry that operates in a second voltage domain different than the first voltage domain, and an isolation region that electrically isolates the first region from the second region in a lateral direction that extends parallel to the first and the second main surfaces. The isolation region includes at least one deep trench isolation barrier, each of which extends vertically from the first main surface to the second main surface. The multi-voltage domain device further includes at least one first capacitor configured to generate an electric field laterally across the isolation region between the first region and the second region.Type: GrantFiled: August 12, 2020Date of Patent: November 23, 2021Inventors: Lars Mueller-Meskamp, Berthold Astegher, Hermann Gruber, Thomas Christian Neidhart
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Patent number: 11038028Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having opposing first and second main surfaces and first and second dopants. A covalent atomic radius of a material of the substrate is i) larger than a covalent atomic radius of the first dopant and smaller than that of the second dopant, or ii) smaller than the covalent atomic radius of the first dopant and larger than that of the second dopant. A vertical extension of the first dopant into the substrate from the first main surface ends at a bottom of a substrate portion at a first vertical distance to the first main surface. The method further includes forming a semiconductor layer on the first main surface, forming semiconductor device elements in the semiconductor layer, and reducing a thickness of the substrate by removing material from the second main surface at least up to the substrate portion.Type: GrantFiled: May 8, 2019Date of Patent: June 15, 2021Assignee: Infineon Technologies AGInventors: Ingo Muri, Johannes Konrad Baumgartl, Oliver Hellmund, Jacob Tillmann Ludwig, Iris Moder, Thomas Christian Neidhart, Gerhard Schmidt, Hans-Joachim Schulze
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Patent number: 11011409Abstract: A semiconductor device includes a first epitaxial layer, a second epitaxial layer disposed below the first epitaxial layer, a conductive layer disposed below and directly contacting the second epitaxial layer, and a plurality of spacers disposed between the second epitaxial layer and the conductive layer. The conductive layer includes a metal. The plurality of spacers include a bulk semiconductor material.Type: GrantFiled: November 26, 2019Date of Patent: May 18, 2021Assignee: Infineon Technologies AGInventors: Oliver Hellmund, Ingo Muri, Johannes Baumgartl, Iris Moder, Thomas Christian Neidhart, Hans-Joachim Schulze
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Publication number: 20200098617Abstract: A semiconductor device includes a first epitaxial layer, a second epitaxial layer disposed below the first epitaxial layer, a conductive layer disposed below and directly contacting the second epitaxial layer, and a plurality of spacers disposed between the second epitaxial layer and the conductive layer. The conductive layer includes a metal. The plurality of spacers include a bulk semiconductor material.Type: ApplicationFiled: November 26, 2019Publication date: March 26, 2020Inventors: Oliver Hellmund, Ingo Muri, Johannes Baumgartl, Iris Moder, Thomas Christian Neidhart, Hans-Joachim Schulze
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Patent number: 10535553Abstract: A semiconductor device includes a trench extending through a semiconductor substrate and an epitaxial layer disposed over a first side of the semiconductor substrate. The epitaxial layer partially fills a portion of the trench. The semiconductor device further includes a back side metal layer disposed over a second side of the semiconductor substrate. The back side metal layer extends into the trench and fills the remaining portion of the trench. The epitaxial layer partially filling the trench contacts the back side metal layer filling the remaining portion within the trench.Type: GrantFiled: April 12, 2018Date of Patent: January 14, 2020Assignee: Infineon Technologies AGInventors: Oliver Hellmund, Ingo Muri, Johannes Baumgartl, Iris Moder, Thomas Christian Neidhart, Hans-Joachim Schulze
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Publication number: 20190348506Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having opposing first and second main surfaces and first and second dopants. A covalent atomic radius of a material of the substrate is i) larger than a covalent atomic radius of the first dopant and smaller than that of the second dopant, or ii) smaller than the covalent atomic radius of the first dopant and larger than that of the second dopant. A vertical extension of the first dopant into the substrate from the first main surface ends at a bottom of a substrate portion at a first vertical distance to the first main surface. The method further includes forming a semiconductor layer on the first main surface, forming semiconductor device elements in the semiconductor layer, and reducing a thickness of the substrate by removing material from the second main surface at least up to the substrate portion.Type: ApplicationFiled: May 8, 2019Publication date: November 14, 2019Inventors: Ingo Muri, Johannes Konrad Baumgartl, Oliver Hellmund, Jacob Tillmann Ludwig, Iris Moder, Thomas Christian Neidhart, Gerhard Schmidt, Hans-Joachim Schulze
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Patent number: 10325804Abstract: In accordance with an embodiment of the present invention, a method of fabricating a semiconductor device includes forming openings partially filled with a sacrificial material, where the openings extend into a semiconductor substrate from a first side. A void region is formed in a central region of the openings. An epitaxial layer is formed over the first side of the semiconductor substrate and the openings, where the epitaxial layer covers the void region. From a second side of the semiconductor substrate opposite to the first side, the semiconductor substrate is thinned to expose the sacrificial material. The sacrificial material in the openings is removed and the epitaxial layer is exposed. A conductive material is deposited on the exposed surface of the epitaxial layer.Type: GrantFiled: December 29, 2017Date of Patent: June 18, 2019Assignee: INFINEON TECHNOLOGIES AGInventors: Oliver Hellmund, Johannes Baumgartl, Iris Moder, Ingo Muri, Thomas Christian Neidhart, Hans-Joachim Schulze
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Publication number: 20180233399Abstract: A semiconductor device includes a trench extending through a semiconductor substrate and an epitaxial layer disposed over a first side of the semiconductor substrate. The epitaxial layer partially fills a portion of the trench. The semiconductor device further includes a back side metal layer disposed over a second side of the semiconductor substrate. The back side metal layer extends into the trench and fills the remaining portion of the trench. The epitaxial layer partially filling the trench contacts the back side metal layer filling the remaining portion within the trench.Type: ApplicationFiled: April 12, 2018Publication date: August 16, 2018Inventors: Oliver Hellmund, Ingo Muri, Johannes Baumgartl, Iris Moder, Thomas Christian Neidhart, Hans-Joachim Schulze
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Publication number: 20180144974Abstract: In accordance with an embodiment of the present invention, a method of fabricating a semiconductor device includes forming openings partially filled with a sacrificial material, where the openings extend into a semiconductor substrate from a first side. A void region is formed in a central region of the openings. An epitaxial layer is formed over the first side of the semiconductor substrate and the openings, where the epitaxial layer covers the void region. From a second side of the semiconductor substrate opposite to the first side, the semiconductor substrate is thinned to expose the sacrificial material. The sacrificial material in the openings is removed and the epitaxial layer is exposed. A conductive material is deposited on the exposed surface of the epitaxial layer.Type: ApplicationFiled: December 29, 2017Publication date: May 24, 2018Inventors: Oliver Hellmund, Johannes Baumgartl, Iris Moder, Ingo Muri, Thomas Christian Neidhart, Hans-Joachim Schulze
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Patent number: 9960076Abstract: A method of fabricating a semiconductor device includes forming trenches filled with a sacrificial material. The trenches extend into a semiconductor substrate from a first side. An epitaxial layer is formed over the first side of the semiconductor substrate and the trenches. From a second side of the semiconductor substrate opposite to the first side, the sacrificial material in the trenches is removed. The trenches are filled with a conductive material.Type: GrantFiled: August 5, 2016Date of Patent: May 1, 2018Assignee: Infineon Technologies AGInventors: Oliver Hellmund, Ingo Muri, Johannes Baumgartl, Iris Moder, Thomas Christian Neidhart, Hans-Joachim Schulze
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Publication number: 20180082882Abstract: A wafer chuck configured to support a wafer during a wafer test procedure comprises a contact portion for supporting the wafer while being in contact with the wafer. The contact portion is made of a conductive material, the conductive material having a melting point larger than 1500° C.Type: ApplicationFiled: September 11, 2017Publication date: March 22, 2018Inventors: Rudolf Zelsacher, Peter Irsigler, Thomas Christian Neidhart
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Publication number: 20180040504Abstract: A method of fabricating a semiconductor device includes forming trenches filled with a sacrificial material. The trenches extend into a semiconductor substrate from a first side. An epitaxial layer is formed over the first side of the semiconductor substrate and the trenches. From a second side of the semiconductor substrate opposite to the first side, the sacrificial material in the trenches is removed. The trenches are filled with a conductive material.Type: ApplicationFiled: August 5, 2016Publication date: February 8, 2018Inventors: Oliver Hellmund, Ingo Muri, Johannes Baumgartl, Iris Moder, Thomas Christian Neidhart, Hans-Joachim Schulze